PERFORCE change 40868 for review
Peter Wemm
peter at FreeBSD.org
Thu Oct 30 13:43:42 PST 2003
http://perforce.freebsd.org/chv.cgi?CH=40868
Change 40868 by peter at peter_daintree on 2003/10/30 13:43:01
p4 integrate -I -b smp_hammer (ie: merge in jhb_acpipci changes)
Affected files ...
.. //depot/projects/hammer/sys/amd64/acpica/madt.c#4 integrate
.. //depot/projects/hammer/sys/amd64/amd64/apic_vector.s#8 integrate
.. //depot/projects/hammer/sys/amd64/amd64/io_apic.c#9 integrate
.. //depot/projects/hammer/sys/amd64/amd64/local_apic.c#12 integrate
.. //depot/projects/hammer/sys/amd64/amd64/mp_machdep.c#16 integrate
.. //depot/projects/hammer/sys/amd64/amd64/mpboot.s#9 integrate
.. //depot/projects/hammer/sys/jhb_notes#6 integrate
Differences ...
==== //depot/projects/hammer/sys/amd64/acpica/madt.c#4 (text+ko) ====
@@ -76,7 +76,7 @@
static int madt_find_cpu(u_int acpi_id, u_int *apic_id);
static int madt_find_interrupt(int intr, void **apic, u_int *pin);
static void *madt_map(vm_paddr_t pa, int offset, vm_offset_t length);
-static void *madt_map_table(vm_paddr_t pa, int offset);
+static void *madt_map_table(vm_paddr_t pa, int offset, const char *sig);
static void madt_parse_apics(APIC_HEADER *entry, void *arg);
static void madt_parse_interrupt_override(INTERRUPT_SOURCE_OVERRIDE *intr);
static void madt_parse_ints(APIC_HEADER *entry, void *arg __unused);
@@ -147,12 +147,16 @@
}
static void *
-madt_map_table(vm_paddr_t pa, int offset)
+madt_map_table(vm_paddr_t pa, int offset, const char *sig)
{
ACPI_TABLE_HEADER *header;
vm_offset_t length;
header = madt_map(pa, offset, sizeof(ACPI_TABLE_HEADER));
+ if (strncmp(header->Signature, sig, 4) != 0) {
+ madt_unmap(header, sizeof(ACPI_TABLE_HEADER));
+ return (NULL);
+ }
length = header->Length;
madt_unmap(header, sizeof(ACPI_TABLE_HEADER));
return (madt_map(pa, offset, length));
@@ -192,7 +196,9 @@
/* XXXTEST */
printf("rsdp_ptr.Pointer.Logical = %p\n",
(void *)rsdp_ptr.Pointer.Logical);
- KASSERT(rsdp_ptr.Pointer.Physical < 1024 * 1024, ("RSDP too high"));
+ printf("rsdp_ptr.Pointer.Physical = 0x%jx\n",
+ (uintmax_t)rsdp_ptr.Pointer.Physical);
+ KASSERT(rsdp_ptr.Pointer.Physical < KERNLOAD, ("RSDP too high"));
rsdp = pmap_mapdev(rsdp_ptr.Pointer.Physical, sizeof(RSDP_DESCRIPTOR));
if (rsdp == NULL) {
#if 0
@@ -204,18 +210,13 @@
/*
* For ACPI < 2.0, use the RSDT. For ACPI >= 2.0, use the XSDT.
- * Note that we are assuming throughout here that pmap_mapdev()
- * is going to give us addresses in the KERNBASE to KERNBASE + 1mb
- * range and as such, that the lengths don't have to be perfect.
- * The XSDT and RSDT are variable length and we don't map in their
- * full length before using the variable length portion. We also
- * don't do any pmap_unmapdev()'s as we assume that they wouldn't
- * do anything anyway.
+ * We map the XSDT and RSDT at page 1 in the crashdump area.
+ * Page 0 is used to map in the headers of candidate ACPI tables.
*/
- if (rsdp->Revision >= 2) {
+ if (rsdp->Revision >= 2 /* && rsdp->RsdtPhysicalAddress == 0 */) {
/* XXXTEST */
printf("XSDT PA = 0x%jx\n", (uintmax_t)rsdp->XsdtPhysicalAddress);
- xsdt = madt_map_table(rsdp->XsdtPhysicalAddress, 1);
+ xsdt = madt_map_table(rsdp->XsdtPhysicalAddress, 1, XSDT_SIG);
if (xsdt == NULL) {
#if 0
if (bootverbose)
@@ -231,8 +232,8 @@
madt_unmap_table(xsdt);
} else {
/* XXXTEST */
- printf("RSDT PA = 0x%jx\n", (uintmax_t)rsdp->XsdtPhysicalAddress);
- rsdt = madt_map_table(rsdp->RsdtPhysicalAddress, 1);
+ printf("RSDT PA = 0x%jx\n", (uintmax_t)rsdp->RsdtPhysicalAddress);
+ rsdt = madt_map_table(rsdp->RsdtPhysicalAddress, 1, RSDT_SIG);
if (rsdt == NULL) {
#if 0
if (bootverbose)
@@ -304,7 +305,8 @@
madt_probe_cpus(void)
{
- madt = madt_map_table(madt_physaddr, 0);
+ madt = madt_map_table(madt_physaddr, 0, APIC_SIG);
+ KASSERT(madt != NULL, ("Unable to re-map MADT"));
madt_walk_table(madt_probe_cpus_handler, NULL);
madt_unmap_table(madt);
madt = NULL;
==== //depot/projects/hammer/sys/amd64/amd64/apic_vector.s#8 (text+ko) ====
@@ -32,7 +32,7 @@
* SUCH DAMAGE.
*
* from: vector.s, 386BSD 0.1 unknown origin
- * $FreeBSD: src/sys/i386/isa/apic_vector.s,v 1.89 2003/07/10 01:02:59 peter Exp $
+ * $FreeBSD: src/sys/i386/isa/apic_vector.s,v 1.90 2003/10/16 10:44:24 bde Exp $
*/
/*
==== //depot/projects/hammer/sys/amd64/amd64/io_apic.c#9 (text+ko) ====
@@ -369,25 +369,28 @@
* Assume that pin 0 on the first IO APIC is an ExtINT pin by
* default. Assume that intpins 1-15 are ISA interrupts and
* use suitable defaults for those. Assume that all other
- * intpins are PCI interrupts.
+ * intpins are PCI interrupts. Enable the ExtINT pin by
+ * default but mask all other pins.
*/
if (intpin->io_vector == 0) {
intpin->io_activehi = 1;
intpin->io_edgetrigger = 1;
intpin->io_vector = VECTOR_EXTINT;
+ intpin->io_masked = 0;
} else if (intpin->io_vector < IOAPIC_ISA_INTS) {
intpin->io_activehi = 1;
intpin->io_edgetrigger = 1;
+ intpin->io_masked = 1;
} else {
intpin->io_activehi = 0;
intpin->io_edgetrigger = 0;
+ intpin->io_masked = 1;
}
/*
- * Start off with this intpin masked and not having a
- * logical cluster destination until it is enabled.
+ * Start off without a logical cluster destination until
+ * the pin is enabled.
*/
- intpin->io_masked = 1;
intpin->io_dest = DEST_NONE;
if (bootverbose) {
printf("ioapic%u: intpin %d -> ", io->io_id, i);
@@ -507,6 +510,7 @@
if (io->io_pins[pin].io_vector < 0)
return (EINVAL);
io->io_pins[pin].io_vector = VECTOR_EXTINT;
+ io->io_pins[pin].io_masked = 0;
io->io_pins[pin].io_edgetrigger = 1;
io->io_pins[pin].io_activehi = 1;
#if 0
@@ -566,7 +570,7 @@
io = (struct ioapic *)cookie;
apic = io->io_addr;
mtx_lock_spin(&icu_lock);
- flags = ioapic_read(apic, IOAPIC_VER) && IOART_VER_VERSION;
+ flags = ioapic_read(apic, IOAPIC_VER) & IOART_VER_VERSION;
STAILQ_INSERT_TAIL(&ioapic_list, io, io_next);
mtx_unlock_spin(&icu_lock);
printf("ioapic%u <Version %u> irqs %u-%u on motherboard\n", io->io_id,
@@ -661,8 +665,9 @@
/*
* Support for mixed-mode interrupt sources. These sources route an ISA
* IRQ through the 8259A's via the ExtINT on pin 0 of the I/O APIC that
- * routes the ISA interrupts. We basically mix and match APIC and atpic
- * functionality to build these interrupt sources.
+ * routes the ISA interrupts. We just ignore the intpins that use this
+ * mode and allow the atpic driver to register its interrupt source for
+ * that IRQ instead.
*/
void
@@ -680,13 +685,11 @@
extint = &io->io_pins[0];
if (extint->io_vector != VECTOR_EXTINT)
panic("Can't find ExtINT pin to route through!");
- if (extint->io_dest == DEST_NONE) {
#if 0
- /* XXXTEST? */
+ /* XXXTEST? */
+ if (extint->io_dest == DEST_NONE)
ioapic_assign_cluster(extint);
#endif
- ioapic_enable_source(&extint->io_intsrc);
- }
}
#endif /* MIXED_MODE */
==== //depot/projects/hammer/sys/amd64/amd64/local_apic.c#12 (text+ko) ====
@@ -75,10 +75,10 @@
struct lapic {
struct lvt la_lvts[LVT_MAX + 1];
- int la_id:8;
- int la_cluster:4;
- int la_cluster_id:2;
- int la_present:1;
+ u_int la_id:8;
+ u_int la_cluster:4;
+ u_int la_cluster_id:2;
+ u_int la_present:1;
} static lapics[MAX_APICID];
/* XXX: should thermal be an NMI? */
==== //depot/projects/hammer/sys/amd64/amd64/mp_machdep.c#16 (text+ko) ====
@@ -24,7 +24,7 @@
*/
#include <sys/cdefs.h>
-__FBSDID("$FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.216 2003/09/10 01:36:48 jhb Exp $");
+__FBSDID("$FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.218 2003/10/24 21:02:26 jhb Exp $");
#include "opt_cpu.h"
#include "opt_kstack_pages.h"
@@ -132,8 +132,8 @@
int cpu_present:1;
int cpu_bsp:1;
} static cpu_info[MAXCPU];
+static int cpu_apic_ids[MAXCPU];
-
static u_int boot_address;
static void set_logical_apic_ids(void);
@@ -234,7 +234,12 @@
void
cpu_mp_start(void)
{
+ int i;
+ /* Initialize the logical ID to APIC ID table. */
+ for (i = 0; i < MAXCPU; i++)
+ cpu_apic_ids[i] = -1;
+
/* Install an inter-CPU IPI for TLB invalidation */
setidt(IPI_INVLTLB, IDTVEC(invltlb), SDT_SYSIGT, SEL_KPL, 0);
setidt(IPI_INVLPG, IDTVEC(invlpg), SDT_SYSIGT, SEL_KPL, 0);
@@ -270,6 +275,7 @@
} else
KASSERT(boot_cpu_id == PCPU_GET(apic_id),
("BSP's APIC ID doesn't match boot_cpu_id"));
+ cpu_apic_ids[0] = boot_cpu_id;
/* Start each Application Processor */
start_all_aps(boot_address);
@@ -364,14 +370,14 @@
panic("cpuid mismatch! boom!!");
}
+ mtx_lock_spin(&ap_boot_mtx);
+
/* Init local apic for irq's */
lapic_setup();
/* Set memory range attributes for this CPU to match the BSP */
mem_range_AP_init();
- mtx_lock_spin(&ap_boot_mtx);
-
smp_cpus++;
CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", PCPU_GET(cpuid));
@@ -476,6 +482,9 @@
continue;
cpu++;
+ /* save APIC ID for this logical ID */
+ cpu_apic_ids[cpu] = apic_id;
+
/* Get per-cpu data */
pc = &__pcpu[cpu];
@@ -564,6 +573,7 @@
u_int16_t *dst16;
u_int32_t *dst32;
+ pmap_kenter(boot_addr + KERNBASE, boot_addr);
for (x = 0; x < size; ++x)
*dst++ = *src++;
@@ -907,7 +917,9 @@
CTR3(KTR_SMP, "%s: cpus: %x ipi: %x", __func__, cpus, ipi);
while ((cpu = ffs(cpus)) != 0) {
cpu--;
- lapic_ipi_vectored(ipi, cpu);
+ KASSERT(cpu_apic_ids[cpu] != -1,
+ ("IPI to non-existent CPU %d", cpu));
+ lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]);
cpus &= ~(1 << cpu);
}
}
==== //depot/projects/hammer/sys/amd64/amd64/mpboot.s#9 (text+ko) ====
@@ -31,7 +31,7 @@
* mpboot.s: FreeBSD machine support for the Intel MP Spec
* multiprocessor systems.
*
- * $FreeBSD: src/sys/i386/i386/mpboot.s,v 1.20 2003/03/30 05:24:52 jake Exp $
+ * $FreeBSD: src/sys/i386/i386/mpboot.s,v 1.21 2003/10/01 23:46:08 peter Exp $
*/
#include <machine/asmacros.h> /* miscellaneous asm macros */
==== //depot/projects/hammer/sys/jhb_notes#6 (text+ko) ====
@@ -17,6 +17,7 @@
- include/mptable.h (from mp_machdep.c)
Files removed in this branch:
+- conf/SMP
- i386/mpapic.c
- isa/intr_machdep.c
- isa/intr_machdep.h
@@ -52,19 +53,25 @@
(this is gross)
- doesn't work when loaded as a module
- UMA needs to be fixed to not need mp_maxid so early
+ - other workaround is to fix mp_maxid at MAXCPU
- move cpu_mp_probe() to SI_SUB_CPU (perhaps shuffle SI of other
SMP sysinits as a result)
- update apic enumerators to probe CPUs later
- have apic enumerators hookup to the apic subsystem after SI_SUB_KLD
maybe SI_ORDER_LAST
+ - disable ACPI module for now
- Need to fix kernel profiling madness. Add an 'etrap' and perhaps
support for bintr2() and eintr2().
+ Implement mixed-mode and use it for IRQ0 unless no ExtINT pin or
NO_MIXED_MODE
+ Add NO_MIXED_MODE option
- Add runtime decision for IRQ0 mixed mode?
-- SMP bogons
- - pmap_lazyfix unhappy with old-style critical sections
++ SMP bogons
+ + doesn't work on 750x
+ + pmap_lazyfix unhappy with old-style critical sections
+- Chokes on scott's dual P3 when looking for ACPI RSDT.
+- Perhaps change the IRQ resource manager such that it starts out empty
+ and a resource entry for each IRQ is added as each IRQ is registered
- Clean up includes in new files.
- Check #ifdef's in new files and look for #if 0 in new code
- Add handling of local APIC ERROR lvt.
@@ -81,6 +88,11 @@
- reimplement lazy masking of interrupts for critical sections w/o bitmasks??
- Enhance acpi_cpu(4) driver to grok SMP at all?
- Rip out CPU halting stuff perhaps and maybe disable MPTable HTT fixup?
+- Support bus_config_intr()?
+ - nexus would have to call intr_config_source()
+ - intr_config_source() would call config_source() method of PIC driver
+ - AT PIC driver could just ignore
+ - APIC driver could reprogram I/O redirection entry
Unrelated to this branch:
- Work on cleaning up nested includes in sys/* headers. According to Bruce,
More information about the p4-projects
mailing list