PERFORCE change 42109 for review
Juli Mallett
jmallett at FreeBSD.org
Tue Nov 11 23:36:45 PST 2003
http://perforce.freebsd.org/chv.cgi?CH=42109
Change 42109 by jmallett at jmallett_dalek on 2003/11/11 23:35:49
Remove unused (mostly MIPS1) stuff, and remove the wired register
init in machdep.c. the tlb code will need to manage such.
Affected files ...
.. //depot/projects/mips/sys/mips/include/cpuregs.h#13 edit
.. //depot/projects/mips/sys/mips/mips/machdep.c#38 edit
Differences ...
==== //depot/projects/mips/sys/mips/include/cpuregs.h#13 (text+ko) ====
@@ -121,7 +121,6 @@
*/
#define MIPS_CR_BR_DELAY 0x80000000
#define MIPS_CR_COP_ERR 0x30000000
-#define MIPS1_CR_EXC_CODE 0x0000003C /* four bits */
#define MIPS3_CR_EXC_CODE 0x0000007C /* five bits */
#define MIPS_CR_IP 0x0000FF00
#define MIPS_CR_EXC_CODE_SHIFT 2
@@ -176,31 +175,6 @@
* MIPS_SR_KU_CUR Current kernel/user mode bit. 1 => user mode.
*/
-#define MIPS1_PARITY_ERR 0x00100000
-#define MIPS1_CACHE_MISS 0x00080000
-#define MIPS1_PARITY_ZERO 0x00040000
-#define MIPS1_SWAP_CACHES 0x00020000
-#define MIPS1_ISOL_CACHES 0x00010000
-
-#define MIPS1_SR_KU_OLD 0x00000020 /* 2nd stacked KU/IE*/
-#define MIPS1_SR_INT_ENA_OLD 0x00000010 /* 2nd stacked KU/IE*/
-#define MIPS1_SR_KU_PREV 0x00000008 /* 1st stacked KU/IE*/
-#define MIPS1_SR_INT_ENA_PREV 0x00000004 /* 1st stacked KU/IE*/
-#define MIPS1_SR_KU_CUR 0x00000002 /* current KU */
-
-/* backwards compatibility */
-#define MIPS_SR_PARITY_ERR MIPS1_PARITY_ERR
-#define MIPS_SR_CACHE_MISS MIPS1_CACHE_MISS
-#define MIPS_SR_PARITY_ZERO MIPS1_PARITY_ZERO
-#define MIPS_SR_SWAP_CACHES MIPS1_SWAP_CACHES
-#define MIPS_SR_ISOL_CACHES MIPS1_ISOL_CACHES
-
-#define MIPS_SR_KU_OLD MIPS1_SR_KU_OLD
-#define MIPS_SR_INT_ENA_OLD MIPS1_SR_INT_ENA_OLD
-#define MIPS_SR_KU_PREV MIPS1_SR_KU_PREV
-#define MIPS_SR_KU_CUR MIPS1_SR_KU_CUR
-#define MIPS_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV
-
/*
* R4000 status register bit definitons,
* where different from r2000/r3000.
@@ -275,9 +249,9 @@
/*
* The bits in the context register.
+ *
+ * XXX XContext
*/
-#define MIPS1_CNTXT_PTE_BASE 0xFFE00000
-#define MIPS1_CNTXT_BAD_VPN 0x001FFFFC
#define MIPS3_CNTXT_PTE_BASE 0xFF800000
#define MIPS3_CNTXT_BAD_VPN2 0x007FFFF0
@@ -365,11 +339,6 @@
#define MIPS_UTLB_MISS_EXC_VEC 0xFFFFFFFF80000000
/*
- * MIPS-1 general exception vector (everything else)
- */
-#define MIPS1_GEN_EXC_VEC 0xFFFFFFFF80000080
-
-/*
* MIPS-III exception vectors
*/
#define MIPS3_XTLB_MISS_EXC_VEC 0xFFFFFFFF80000080
@@ -540,7 +509,6 @@
#define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000
#define MIPS_FPU_COND_BIT 0x00800000
#define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */
-#define MIPS1_FPC_MBZ_BITS 0xff7c0000
#define MIPS3_FPC_MBZ_BITS 0xfe7c0000
@@ -550,109 +518,15 @@
#define MIPS_OPCODE_SHIFT 26
#define MIPS_OPCODE_C1 0x11
-
-/*
- * The low part of the TLB entry.
- */
-#define MIPS1_TLB_PFN 0xfffff000
-#define MIPS1_TLB_NON_CACHEABLE_BIT 0x00000800
-#define MIPS1_TLB_DIRTY_BIT 0x00000400
-#define MIPS1_TLB_VALID_BIT 0x00000200
-#define MIPS1_TLB_GLOBAL_BIT 0x00000100
-
-#define MIPS3_TLB_PFN 0x3fffffc0
-#define MIPS3_TLB_ATTR_MASK 0x00000038
-#define MIPS3_TLB_ATTR_SHIFT 3
-#define MIPS3_TLB_DIRTY_BIT 0x00000004
-#define MIPS3_TLB_VALID_BIT 0x00000002
-#define MIPS3_TLB_GLOBAL_BIT 0x00000001
-
-#define MIPS1_TLB_PHYS_PAGE_SHIFT 12
-#define MIPS3_TLB_PHYS_PAGE_SHIFT 6
-#define MIPS1_TLB_PF_NUM MIPS1_TLB_PFN
-#define MIPS3_TLB_PF_NUM MIPS3_TLB_PFN
-#define MIPS1_TLB_MOD_BIT MIPS1_TLB_DIRTY_BIT
-#define MIPS3_TLB_MOD_BIT MIPS3_TLB_DIRTY_BIT
-
-/*
- * MIPS3_TLB_ATTR values - coherency algorithm:
- * 0: cacheable, noncoherent, write-through, no write allocate
- * 1: cacheable, noncoherent, write-through, write allocate
- * 2: uncached
- * 3: cacheable, noncoherent, write-back (noncoherent)
- * 4: cacheable, coherent, write-back, exclusive (exclusive)
- * 5: cacheable, coherent, write-back, exclusive on write (sharable)
- * 6: cacheable, coherent, write-back, update on write (update)
- * 7: uncached, accelerated (gather STORE operations)
- */
-#define MIPS3_TLB_ATTR_WT 0 /* IDT */
-#define MIPS3_TLB_ATTR_WT_WRITEALLOCATE 1 /* IDT */
-#define MIPS3_TLB_ATTR_UNCACHED 2 /* R4000/R4400, IDT */
-#define MIPS3_TLB_ATTR_WB_NONCOHERENT 3 /* R4000/R4400, IDT */
-#define MIPS3_TLB_ATTR_WB_EXCLUSIVE 4 /* R4000/R4400 */
-#define MIPS3_TLB_ATTR_WB_SHARABLE 5 /* R4000/R4400 */
-#define MIPS3_TLB_ATTR_WB_UPDATE 6 /* R4000/R4400 */
-#define MIPS4_TLB_ATTR_UNCACHED_ACCELERATED 7 /* R10000 */
-
-
/*
- * The high part of the TLB entry.
- */
-#define MIPS1_TLB_VPN 0xfffff000
-#define MIPS1_TLB_PID 0x00000fc0
-#define MIPS1_TLB_PID_SHIFT 6
-
-#define MIPS3_TLB_VPN2 0xffffe000
-#define MIPS3_TLB_ASID 0x000000ff
-
-#define MIPS1_TLB_VIRT_PAGE_NUM MIPS1_TLB_VPN
-#define MIPS3_TLB_VIRT_PAGE_NUM MIPS3_TLB_VPN2
-#define MIPS3_TLB_PID MIPS3_TLB_ASID
-#define MIPS_TLB_VIRT_PAGE_SHIFT 12
-
-/*
- * r3000: shift count to put the index in the right spot.
- */
-#define MIPS1_TLB_INDEX_SHIFT 8
-
-/*
- * The first TLB that write random hits.
- */
-#define MIPS1_TLB_FIRST_RAND_ENTRY 8
-#define MIPS3_TLB_WIRED_UPAGES 1
-
-/*
* The number of process id entries.
*/
-#define MIPS1_TLB_NUM_PIDS 64
#define MIPS3_TLB_NUM_ASIDS 256
-/*
- * Patch codes to hide CPU design differences between MIPS1 and MIPS3.
- */
-
/* XXX simonb: this is before MIPS3_PLUS is defined (and is ugly!) */
-#if !(defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \
- && defined(MIPS1) /* XXX simonb must be neater! */
-#define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT
-#define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS
-#endif
-
-#if (defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)) \
- && !defined(MIPS1) /* XXX simonb must be neater! */
#define MIPS_TLB_PID_SHIFT 0
#define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_ASIDS
-#endif
-
-
-#if !defined(MIPS_TLB_PID_SHIFT)
-#define MIPS_TLB_PID_SHIFT \
- ((MIPS_HAS_R4K_MMU) ? 0 : MIPS1_TLB_PID_SHIFT)
-
-#define MIPS_TLB_NUM_PIDS \
- ((MIPS_HAS_R4K_MMU) ? MIPS3_TLB_NUM_ASIDS : MIPS1_TLB_NUM_PIDS)
-#endif
/*
* CPU processor revision IDs for company ID == 0 (non mips32/64 chips)
==== //depot/projects/mips/sys/mips/mips/machdep.c#38 (text+ko) ====
@@ -738,7 +738,6 @@
case CPU_ARCH_MIPS64:
mips_wr_wired(0);
tlb_invalidate_all();
- mips_wr_wired(MIPS3_TLB_WIRED_UPAGES);
mips64_vector_init();
break;
default:
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