PERFORCE change 44026 for review

[John Baldwin]

http://perforce.freebsd.org/chv.cgi?CH=44026

Change 44026 by jhb at jhb_laptop on 2003/12/17 08:51:27

	Another (but untested) patch from my laptop that tries to cleanup
	the smp rendezvous code slightly in case sending an IPI doesn't
	force the caches on other CPUs to be up to date with no stale values.
	Basically, remove some bogus membars, add some appropriate ones,
	and add an extra wait at the beginning with membars to try and make
	sure we are up to date.

Affected files ...

.. //depot/projects/smpng/sys/kern/subr_smp.c#24 edit

Differences ...

==== //depot/projects/smpng/sys/kern/subr_smp.c#24 (text+ko) ====

@@ -94,7 +94,7 @@
 static void (*smp_rv_action_func)(void *arg);
 static void (*smp_rv_teardown_func)(void *arg);
 static void *smp_rv_func_arg;
-static volatile int smp_rv_waiters[2];
+static volatile int smp_rv_waiters[3];
 static struct mtx smp_rv_mtx;
 
 /*
@@ -279,19 +279,23 @@
 smp_rendezvous_action(void)
 {
 
+	/* Ensure we have up-to-date values. */
+	atomic_add_acq_int(&smp_rv_waiters[0], 1);
+	while (smp_rv_waiters[0] < mp_ncpus)
+		;	/* nothing */
 	/* setup function */
 	if (smp_rv_setup_func != NULL)
 		smp_rv_setup_func(smp_rv_func_arg);
 	/* spin on entry rendezvous */
-	atomic_add_int(&smp_rv_waiters[0], 1);
-	while (atomic_load_acq_int(&smp_rv_waiters[0]) < mp_ncpus)
+	atomic_add_int(&smp_rv_waiters[1], 1);
+	while (smp_rv_waiters[0] < mp_ncpus)
 		;	/* nothing */
 	/* action function */
 	if (smp_rv_action_func != NULL)
 		smp_rv_action_func(smp_rv_func_arg);
 	/* spin on exit rendezvous */
-	atomic_add_int(&smp_rv_waiters[1], 1);
-	while (atomic_load_acq_int(&smp_rv_waiters[1]) < mp_ncpus)
+	atomic_add_int(&smp_rv_waiters[2], 1);
+	while (smp_rv_waiters[1] < mp_ncpus)
 		;	/* nothing */
 	/* teardown function */
 	if (smp_rv_teardown_func != NULL)
@@ -323,8 +327,9 @@
 	smp_rv_action_func = action_func;
 	smp_rv_teardown_func = teardown_func;
 	smp_rv_func_arg = arg;
-	smp_rv_waiters[0] = 0;
 	smp_rv_waiters[1] = 0;
+	smp_rv_waiters[2] = 0;
+	atomic_store_rel_int(&smp_rv_waiters[0], 0);
 
 	/* signal other processors, which will enter the IPI with interrupts off */
 	ipi_all_but_self(IPI_RENDEZVOUS);