PERFORCE change 37258 for review
Marcel Moolenaar
marcel at FreeBSD.org
Sat Aug 30 23:35:50 PDT 2003
http://perforce.freebsd.org/chv.cgi?CH=37258
Change 37258 by marcel at marcel_nfs on 2003/08/30 23:35:11
Implement UART_IPEND() and UART_TRANSMIT(). With only
these two functions we can boot single- and multi-
user. Of course the console is pretty much useless
for anything other than output, but at least I know
transmit interrupts work.
Next step: UART_GETSIG() and UART_SETSIG() so that
getty(8) works, followed by UART_RECEIVE() to allow
me to actually login in.
I'm pretty happy with how easily one can get new
hardware to work. I think it means that the hardware
interface has the right (or at least a workable)
abstraction...
Affected files ...
.. //depot/projects/uart/dev/uart/uart_dev_z8530.c#7 edit
.. //depot/projects/uart/dev/uart/uart_dev_z8530.h#4 edit
Differences ...
==== //depot/projects/uart/dev/uart/uart_dev_z8530.c#7 (text+ko) ====
@@ -187,8 +187,6 @@
z8530_param(bas, baudrate, databits, stopbits, parity,
TPC_DTR | TPC_RTS);
-
- /* WR1, WR15 */
}
static void
@@ -264,6 +262,13 @@
.uc_rclk = DEFAULT_RCLK
};
+#define SIGCHG(c, i, s, d) \
+ if (c) { \
+ i |= (i & s) ? s : s | d; \
+ } else { \
+ i = (i & s) ? (i & ~s) | d : i; \
+ }
+
static int
z8530_bus_attach(struct uart_softc *sc)
{
@@ -273,9 +278,13 @@
if (sc->sc_sysdev == NULL)
z8530_init(bas, 9600, 8, 1, UART_PARITY_NONE);
- sc->sc_rxfifosz = 32;
- sc->sc_txfifosz = 32;
+ sc->sc_rxfifosz = 1;
+ sc->sc_txfifosz = 1;
+ uart_setmreg(bas, WR_IC, IC_BRK | IC_CTS | IC_DCD);
+ uart_setmreg(bas, WR_IDT, IDT_TIE | IDT_RIA);
+ uart_setmreg(bas, WR_IV, 0);
+ uart_barrier(bas);
return (0);
}
@@ -303,8 +312,35 @@
static int
z8530_bus_ipend(struct uart_softc *sc)
{
+ struct uart_bas *bas;
+ int ipend;
+ uint8_t bes, src;
- return (0);
+ bas = &sc->sc_bas;
+ ipend = 0;
+ uart_setreg(bas, REG_CTRL, CR_RSTIUS);
+ uart_barrier(bas);
+ bes = uart_getmreg(bas, RR_BES);
+ if (bes & BES_BRK) {
+ uart_setreg(bas, REG_CTRL, CR_RSTXSI);
+ ipend |= UART_IPEND_BREAK;
+ }
+ if (bes & BES_TXE) {
+ uart_setreg(bas, REG_CTRL, CR_RSTTXI);
+ ipend |= UART_IPEND_TXIDLE;
+ }
+ if (bes & BES_RXA)
+ ipend |= UART_IPEND_RXREADY;
+ SIGCHG(bes & BES_CTS, sc->sc_hwsig, UART_SIG_CTS, UART_SIG_DCTS);
+ SIGCHG(bes & BES_DCD, sc->sc_hwsig, UART_SIG_DCD, UART_SIG_DDCD);
+ if (sc->sc_hwsig & UART_SIGMASK_DELTA)
+ ipend |= UART_IPEND_SIGCHG;
+ src = uart_getmreg(bas, RR_SRC);
+ if (src & SRC_OVR) {
+ uart_setreg(bas, REG_CTRL, CR_RSTERR);
+ ipend |= UART_IPEND_OVERRUN;
+ }
+ return (ipend);
}
static int
@@ -339,7 +375,7 @@
static int
z8530_bus_receive(struct uart_softc *sc)
{
-
+
return (0);
}
@@ -353,6 +389,13 @@
static int
z8530_bus_transmit(struct uart_softc *sc)
{
+ struct uart_bas *bas;
+ bas = &sc->sc_bas;
+ while (!(uart_getmreg(bas, RR_BES) & BES_TXE))
+ ;
+ uart_setreg(bas, REG_DATA, sc->sc_txbuf[0]);
+ uart_barrier(bas);
+ sc->sc_txbusy = 1;
return (0);
}
==== //depot/projects/uart/dev/uart/uart_dev_z8530.h#4 (text+ko) ====
@@ -40,7 +40,7 @@
/* Write registers. */
#define WR_CR 0 /* Command Register. */
-#define WR_IDTM 1 /* Interrupt and Data Transfer Mode. */
+#define WR_IDT 1 /* Interrupt and Data Transfer Mode. */
#define WR_IV 2 /* Interrupt Vector (shared). */
#define WR_RPC 3 /* Receive Parameters and Control. */
#define WR_MPM 4 /* Miscellaneous Parameters and Modes. */
@@ -101,6 +101,65 @@
#define CMC_TRXC_XMIT 0x01 /* -TRxC from Tx clock. */
#define CMC_TRXC_XTAL 0x00 /* -TRxC from XTAL. */
+/* Command Register (WR0). */
+#define CR_RSTTXU 0xc0 /* Reset Tx. Underrun/EOM. */
+#define CR_RSTTXCRC 0x80 /* Reset Tx. CRC. */
+#define CR_RSTRXCRC 0x40 /* Reset Rx. CRC. */
+#define CR_RSTIUS 0x38 /* Reset Int. Under Service. */
+#define CR_RSTERR 0x30 /* Error Reset. */
+#define CR_RSTTXI 0x28 /* Reset Tx. Int. */
+#define CR_ENARXI 0x20 /* Enable Rx. Int. */
+#define CR_ABORT 0x18 /* Send Abort. */
+#define CR_RSTXSI 0x10 /* Reset Ext/Status Int. */
+
+/* Extended Feature and FIFO Control (WR7 prime). */
+#define EFC_ERE 0x40 /* Extended Read Enable. */
+#define EFC_FE 0x20 /* Transmit FIFO Empty. */
+#define EFC_RQT 0x10 /* Request Timing. */
+#define EFC_FHF 0x08 /* Receive FIFO Half Full. */
+#define EFC_RTS 0x04 /* Auto RTS Deactivation. */
+#define EFC_EOM 0x02 /* Auto EOM Reset. */
+#define EFC_FLAG 0x01 /* Auto SDLC Flag on Tx. */
+
+/* Interrupt Control (WR15). */
+#define IC_BRK 0x80 /* Break (Abort) IE. */
+#define IC_TXU 0x40 /* Tx Underrun IE. */
+#define IC_CTS 0x20 /* CTS IE. */
+#define IC_SYNC 0x10 /* Sync IE. */
+#define IC_DCD 0x08 /* DCD IE. */
+#define IC_FIFO 0x04 /* SDLC FIFO Enable. */
+#define IC_ZC 0x02 /* Zero Count IE. */
+#define IC_EF 0x01 /* Extended Feature Enable. */
+
+/* Interrupt and Data Transfer Mode (WR1). */
+#define IDT_WRE 0x80 /* Wait/DMA Request Enable. */
+#define IDT_REQ 0x40 /* DMA Request. */
+#define IDT_WRR 0x20 /* Wait/DMA Reuest on Receive. */
+#define IDT_RISC 0x18 /* Rx Int. on Special Condition Only. */
+#define IDT_RIA 0x10 /* Rx Int. on All Characters. */
+#define IDT_RIF 0x08 /* Rx Int. on First Character. */
+#define IDT_PSC 0x04 /* Parity is Special Condition. */
+#define IDT_TIE 0x02 /* Tx Int. Enable. */
+#define IDT_XIE 0x01 /* Ext. Int. Enable. */
+
+/* Interrupt Pending (RR3). */
+#define IP_RIA 0x20 /* Rx. Int. ch. A. */
+#define IP_TIA 0x10 /* Tx. Int. ch. A. */
+#define IP_SIA 0x08 /* Ext/Status Int. ch. A. */
+#define IP_RIB 0x04 /* Rx. Int. ch. B. */
+#define IP_TIB 0x02 /* Tx. Int. ch. B. */
+#define IP_SIB 0x01 /* Ext/Status Int. ch. B. */
+
+/* Interrupt Vector Status Low (RR2). */
+#define IV_SCA 0x0e /* Special Condition ch. A. */
+#define IV_RAA 0x0c /* Receive Available ch. A. */
+#define IV_XSA 0x0a /* External/Status Change ch. A. */
+#define IV_TEA 0x08 /* Transmitter Empty ch. A. */
+#define IV_SCB 0x06 /* Special Condition ch. B. */
+#define IV_RAB 0x04 /* Receive Available ch. B. */
+#define IV_XSB 0x02 /* External/Status Change ch. B. */
+#define IV_TEB 0x00 /* Transmitter Empty ch. B. */
+
/* Miscellaneous Control Bits part 1 (WR10). */
#define MCB1_CRC1 0x80 /* CRC presets to 1. */
#define MCB1_FM0 0x60 /* FM0 Encoding. */
@@ -138,7 +197,7 @@
#define MIC_NV 0x02 /* No Vector. */
#define MIC_VIS 0x01 /* Vector Includes Status. */
-/* Transmit/Receive Miscellaneous Parameters and Modes. */
+/* Transmit/Receive Miscellaneous Parameters and Modes (WR4). */
#define MPM_CM64 0xc0 /* X64 Clock Mode. */
#define MPM_CM32 0x80 /* X32 Clock Mode. */
#define MPM_CM16 0x40 /* X16 Clock Mode. */
@@ -166,6 +225,16 @@
#define RPC_LI 0x02 /* SYNC Character Load Inhibit */
#define RPC_RXE 0x01 /* Receiver Enable */
+/* Special Receive Condition (RR1). */
+#define SRC_EOF 0x80 /* End Of Frame. */
+#define SRC_FE 0x40 /* Framing Error. */
+#define SRC_OVR 0x20 /* Rx. Overrun. */
+#define SRC_PE 0x10 /* Parity Error. */
+#define SRC_RC0 0x08 /* Residue Code 0. */
+#define SRC_RC1 0x04 /* Residue Code 1. */
+#define SRC_RC2 0x02 /* Residue Code 2. */
+#define SRC_AS 0x01 /* All Sent. */
+
/* Transmit Parameter and Control (WR5). */
#define TPC_DTR 0x80 /* DTR. */
#define TPC_TB8 0x60 /* 8 databits. */
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