PERFORCE change 37249 for review
Marcel Moolenaar
marcel at FreeBSD.org
Sat Aug 30 16:09:46 PDT 2003
http://perforce.freebsd.org/chv.cgi?CH=37249
Change 37249 by marcel at marcel_nfs on 2003/08/30 16:09:42
o Properly define DEFAULT_RCLK for the one system I know
about.
o Add uart_getmreg() and uart_setmreg() to abstract the
multiplexing of the registers. This cannot be moved to
uart.h, because it's hardware specific.
o Implement z8530_divisor() to calculate the BRG time
constant from the baudrate.
o Implement z8530_param() to set the serial line mode.
Note that the RTS and DTR signals need to be given to
this function because we cannot obtain their current
value and we write the register that defines them. We
simply move the problem to the caller.
o Implement z8530_init() to initialize a channel suitable
for low-level console handling. We only need to add the
initialization of interrupts to be complete.
o Implement z8530_bus_param() in terms of z8530_param).
We only need to preserve RTS and DTR by keeping their
state in the softc.
o Implement z8530_bus_probe(). Uses z8530_probe(), but
otherwise just sets the device description.
Replace the copied uart_dev_z8530.h file with my own. The
register constants were inconsistent with the register bit
definitions. The bits had the WRx or RRx prefix, where x
is the register number, but it didn't correlate to the
constant used for the register itself.
My constants are much more cryptic. You probably wouldn't
understand much of them (BES_CTS, BES_DCD and the likes
should not be too hard to guess), without the datasheet.
Then again, you cannot understand the behaviour of the
chip without the datasheet anyway, so it's in perfect
harmony. More constants are added on a need to have basis.
We're ready to flesh-out the hardware I/F methods used for
regular multi-user operation.
Affected files ...
.. //depot/projects/uart/dev/uart/uart_dev_z8530.c#6 edit
.. //depot/projects/uart/dev/uart/uart_dev_z8530.h#3 edit
Differences ...
==== //depot/projects/uart/dev/uart/uart_dev_z8530.c#6 (text+ko) ====
@@ -40,7 +40,104 @@
#include "uart_if.h"
-#define DEFAULT_RCLK 1843200
+#define DEFAULT_RCLK 307200
+
+#define IS_CHANNEL_A(bas) (((bas)->bsh & 7) != 0)
+#define IS_CHANNEL_B(bas) (((bas)->bsh & 7) == 0)
+
+/* Multiplexed I/O. */
+static __inline void
+uart_setmreg(struct uart_bas *bas, int reg, int val)
+{
+
+ uart_setreg(bas, REG_CTRL, reg);
+ uart_barrier(bas);
+ uart_setreg(bas, REG_CTRL, val);
+}
+
+static __inline uint8_t
+uart_getmreg(struct uart_bas *bas, int reg)
+{
+
+ uart_setreg(bas, REG_CTRL, reg);
+ uart_barrier(bas);
+ return (uart_getreg(bas, REG_CTRL));
+}
+
+static int
+z8530_divisor(int rclk, int baudrate)
+{
+ int act_baud, divisor, error;
+
+ if (baudrate == 0)
+ return (0);
+
+ divisor = (rclk + baudrate) / (baudrate << 1) - 2;
+ if (divisor >= 65536)
+ return (0);
+ act_baud = rclk / 2 / (divisor + 2);
+
+ /* 10 times error in percent: */
+ error = ((act_baud - baudrate) * 2000 / baudrate + 1) >> 1;
+
+ /* 3.0% maximum error tolerance: */
+ if (error < -30 || error > 30)
+ return (0);
+
+ return (divisor);
+}
+
+static int
+z8530_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
+ int parity, int tpc)
+{
+ int divisor;
+ uint8_t rpc, mpm;
+
+ rpc = RPC_RXE;
+ mpm = MPM_CM16;
+ tpc = TPC_TXE | (tpc & (TPC_DTR | TPC_RTS));
+
+ if (databits >= 8) {
+ rpc |= RPC_RB8;
+ tpc |= TPC_TB8;
+ } else if (databits == 7) {
+ rpc |= RPC_RB7;
+ tpc |= TPC_TB7;
+ } else if (databits == 6) {
+ rpc |= RPC_RB6;
+ tpc |= TPC_TB6;
+ } else {
+ rpc |= RPC_RB5;
+ tpc |= TPC_TB5;
+ }
+ mpm |= (stopbits > 1) ? MPM_SB2 : MPM_SB1;
+ switch (parity) {
+ case UART_PARITY_EVEN: mpm |= MPM_PE | MPM_EVEN; break;
+ case UART_PARITY_NONE: break;
+ case UART_PARITY_ODD: mpm |= MPM_PE; break;
+ default: return (EINVAL);
+ }
+
+ /* Set baudrate. */
+ if (baudrate > 0) {
+ divisor = z8530_divisor(bas->rclk, baudrate);
+ if (divisor == 0)
+ return (EINVAL);
+ uart_setmreg(bas, WR_TCL, divisor & 0xff);
+ uart_barrier(bas);
+ uart_setmreg(bas, WR_TCH, (divisor >> 8) & 0xff);
+ uart_barrier(bas);
+ }
+
+ uart_setmreg(bas, WR_RPC, rpc);
+ uart_barrier(bas);
+ uart_setmreg(bas, WR_MPM, mpm);
+ uart_barrier(bas);
+ uart_setmreg(bas, WR_TPC, tpc);
+ uart_barrier(bas);
+ return (0);
+}
/*
* Low-level UART interface.
@@ -75,6 +172,23 @@
if (bas->rclk == 0)
bas->rclk = DEFAULT_RCLK;
+
+ /* Assume we don't need to perform a full hardware reset. */
+ uart_setmreg(bas, WR_MIC, ((IS_CHANNEL_A(bas)) ? MIC_CRA : MIC_CRB) |
+ MIC_MIE | MIC_NV);
+ uart_barrier(bas);
+ /* Set clock sources and enable BRG. */
+ uart_setmreg(bas, WR_CMC, CMC_RC_BRG | CMC_TC_BRG);
+ uart_setmreg(bas, WR_MCB2, MCB2_PCLK | MCB2_BRGE);
+ uart_barrier(bas);
+ /* Set data encoding. */
+ uart_setmreg(bas, WR_MCB1, MCB1_NRZ);
+ uart_barrier(bas);
+
+ z8530_param(bas, baudrate, databits, stopbits, parity,
+ TPC_DTR | TPC_RTS);
+
+ /* WR1, WR15 */
}
static void
@@ -86,7 +200,7 @@
z8530_putc(struct uart_bas *bas, int c)
{
- while (!(uart_getreg(bas, REG_CTRL) & RR0_TX_READY))
+ while (!(uart_getmreg(bas, RR_BES) & BES_TXE))
;
uart_setreg(bas, REG_DATA, c);
uart_barrier(bas);
@@ -96,7 +210,7 @@
z8530_poll(struct uart_bas *bas)
{
- if (!(uart_getreg(bas, REG_CTRL) & RR0_RX_READY))
+ if (!(uart_getmreg(bas, RR_BES) & BES_RXA))
return (-1);
return (uart_getreg(bas, REG_DATA));
}
@@ -105,7 +219,7 @@
z8530_getc(struct uart_bas *bas)
{
- while (!(uart_getreg(bas, REG_CTRL) & RR0_RX_READY))
+ while (!(uart_getmreg(bas, RR_BES) & BES_RXA))
;
return (uart_getreg(bas, REG_DATA));
}
@@ -153,6 +267,14 @@
static int
z8530_bus_attach(struct uart_softc *sc)
{
+ struct uart_bas *bas;
+
+ bas = &sc->sc_bas;
+ if (sc->sc_sysdev == NULL)
+ z8530_init(bas, 9600, 8, 1, UART_PARITY_NONE);
+
+ sc->sc_rxfifosz = 32;
+ sc->sc_txfifosz = 32;
return (0);
}
@@ -189,14 +311,28 @@
z8530_bus_param(struct uart_softc *sc, int baudrate, int databits,
int stopbits, int parity)
{
+ struct uart_bas *bas;
- return (0);
+ bas = &sc->sc_bas;
+ return (z8530_param(bas, baudrate, databits, stopbits, parity, 0));
}
static int
z8530_bus_probe(struct uart_softc *sc)
{
+ char buf[80];
+ const char *ch;
+ int error;
+ error = z8530_probe(&sc->sc_bas);
+ if (error)
+ return (error);
+
+ /* Assume the address range is naturally aligned. */
+ ch = IS_CHANNEL_A(&sc->sc_bas) ? "A" : "B";
+
+ snprintf(buf, sizeof(buf), "z8530, channel %s", ch);
+ device_set_desc_copy(sc->sc_dev, buf);
return (0);
}
==== //depot/projects/uart/dev/uart/uart_dev_z8530.h#3 (text+ko) ====
@@ -1,93 +1,33 @@
-/* $NetBSD: z8530reg.h,v 1.8 1996/12/13 21:02:39 gwr Exp $ */
-
/*
- * Copyright (c) 1992, 1993
- * The Regents of the University of California. All rights reserved.
- *
- * This software was developed by the Computer Systems Engineering group
- * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
- * contributed to Berkeley.
+ * Copyright (c) 2003 Marcel Moolenaar
+ * All rights reserved.
*
- * All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed by the University of
- * California, Lawrence Berkeley Laboratory.
- *
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
+ *
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
- * 3. All advertising materials mentioning features or use of this software
- * must display the following acknowledgement:
- * This product includes software developed by the University of
- * California, Berkeley and its contributors.
- * 4. Neither the name of the University nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
*
- * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * @(#)zsreg.h 8.1 (Berkeley) 6/11/93
- *
- * $FreeBSD: src/sys/dev/zs/z8530reg.h,v 1.2 2003/01/08 23:36:16 jake Exp $
+ * $FreeBSD$
*/
-/*
- * Zilog SCC registers, as implemented on the Sun-4c.
- *
- * Each Z8530 implements two channels (called `a' and `b').
- *
- * The damnable chip was designed to fit on Z80 I/O ports, and thus
- * has everything multiplexed out the wazoo. We have to select
- * a register, then read or write the register, and so on. Worse,
- * the parameter bits are scattered all over the register space.
- * This thing is full of `miscellaneous' control registers.
- *
- * Worse yet, the registers have incompatible functions on read
- * and write operations. We describe the registers below according
- * to whether they are `read registers' (RR) or `write registers' (WR).
- * As if this were not enough, some of the channel B status bits show
- * up in channel A, and vice versa. The blasted thing shares write
- * registers 2 and 9 across both channels, and reads registers 2 and 3
- * differently for the two channels. We can, however, ignore this much
- * of the time.
- *
- * This file also includes flags for the Z85C30 and Z85230 enhanced scc.
- * The CMOS 8530 includes extra SDLC functionality, and is used in a
- * number of Macs (often in the Z85C80, an 85C30 combined w/ a SCSI
- * controller). -wrs
- *
- * Some of the names in this files were chosen to make the hsis driver
- * work unchanged (which means that they will match some in SunOS).
- *
- * `S.C.' stands for Special Condition, which is any of these:
- * receiver overrun (aka silo overflow)
- * framing error (missing stop bit, etc)
- * end of frame (in synchronous modes)
- * parity error (when `parity error is S.C.' is set)
- *
- * Registers with only a single `numeric value' get a name.
- * Other registers hold bits and are only numbered; the bit
- * definitions imply the register number (see below).
- *
- * We never use the receive and transmit data registers as
- * indirects (choosing instead the zc_data register), so they
- * are not defined here.
- */
+#ifndef _DEV_UART_DEV_Z8530_H_
+#define _DEV_UART_DEV_Z8530_H_
/*
* Channel B control: 0
@@ -98,365 +38,144 @@
#define REG_CTRL 0
#define REG_DATA 2
-#define RR_IVEC 2 /* interrupt vector (channel 0) */
-#define RR_IPEND 3 /* interrupt pending (ch. 0 only) */
-#define RR_TXSYNC 6 /* sync transmit char (monosync mode) */
-#define RR_RXSYNC 7 /* sync receive char (monosync mode) */
-#define RR_SYNCLO 6 /* sync low byte (bisync mode) */
-#define RR_SYNCHI 7 /* sync high byte (bisync mode) */
-#define RR_SDLC_ADDR 6 /* SDLC address (SDLC mode) */
-#define RR_SDLC_FLAG 7 /* SDLC flag 0x7E (SDLC mode) */
-#define RR_BAUDLO 12 /* baud rate generator (low half) */
-#define RR_BAUDHI 13 /* baud rate generator (high half) */
-#define RR_ENHANCED 14 /* read address of WR7' - yes, it's not 7!*/
+/* Write registers. */
+#define WR_CR 0 /* Command Register. */
+#define WR_IDTM 1 /* Interrupt and Data Transfer Mode. */
+#define WR_IV 2 /* Interrupt Vector (shared). */
+#define WR_RPC 3 /* Receive Parameters and Control. */
+#define WR_MPM 4 /* Miscellaneous Parameters and Modes. */
+#define WR_TPC 5 /* Transmit Parameters and Control. */
+#define WR_SCAF 6 /* Sync Character or (SDLC) Address Field. */
+#define WR_SCF 7 /* Sync Character or (SDCL) Flag. */
+#define WR_EFC 7 /* Extended Feature and FIFO Control. */
+#define WR_TB 8 /* Transmit Buffer. */
+#define WR_MIC 9 /* Master Interrupt Control (shared). */
+#define WR_MCB1 10 /* Miscellaneous Control Bits (part 1 :-). */
+#define WR_CMC 11 /* Clock Mode Control. */
+#define WR_TCL 12 /* BRG Time Constant Low. */
+#define WR_TCH 13 /* BRG Time Constant High. */
+#define WR_MCB2 14 /* Miscellaneous Control Bits (part 2 :-). */
+#define WR_IC 15 /* Interrupt Control. */
-#define WR_IVEC 2 /* interrupt vector (shared) */
-#define WR_TXSYNC 6 /* sync transmit char (monosync mode) */
-#define WR_RXSYNC 7 /* sync receive char (monosync mode) */
-#define WR_SYNCLO 6 /* sync low byte (bisync mode) */
-#define WR_SYNCHI 7 /* sync high byte (bisync mode) */
-#define WR_SDLC_ADDR 6 /* SDLC address (SDLC mode) */
-#define WR_SDLC_FLAG 7 /* SDLC flag 0x7E (SDLC mode) */
-#define WR_BAUDLO 12 /* baud rate generator (low half) */
-#define WR_BAUDHI 13 /* baud rate generator (high half) */
-#define WR_ENHANCED 7 /* write address of WR7' */
+/* Read registers. */
+#define RR_BES 0 /* Buffer and External Status. */
+#define RR_SRC 1 /* Special Receive Condition. */
+#define RR_IV 2 /* Interrupt Vector. */
+#define RR_IP 3 /* Interrupt Pending (ch A only). */
+#define RR_MPM 4 /* Miscellaneous Parameters and Modes. */
+#define RR_TPC 5 /* Transmit Parameters and Control. */
+#define RR_BCL 6 /* Byte Count Low. */
+#define RR_BCH 7 /* Byte Count High. */
+#define RR_RB 8 /* Receive Buffer. */
+#define RR_RPC 9 /* Receive Parameters and Contro. */
+#define RR_MSB 10 /* Miscellaneous Status Bits. */
+#define RR_MCB1 11 /* Miscellaneous Control Bits (part 1). */
+#define RR_TCL 12 /* BRG Time Constant Low. */
+#define RR_TCH 13 /* BRG Time Constant High. */
+#define RR_EFC 14 /* Extended Feature and FIFO Control. */
+#define RR_IC 15 /* Interrupt Control. */
-/*
- * Registers 0 through 7 may be written with any one of the 8 command
- * modifiers, and/or any one of the 4 reset modifiers, defined below.
- * To write registers 8 through 15, however, the command modifier must
- * always be `point high'. Rather than track this bizzareness all over
- * the driver, we try to avoid using any modifiers, ever (but they are
- * defined here if you want them).
- */
-#define ZSM_RESET_TXUEOM 0xc0 /* reset xmit underrun / eom latch */
-#define ZSM_RESET_TXCRC 0x80 /* reset xmit crc generator */
-#define ZSM_RESET_RXCRC 0x40 /* reset recv crc checker */
-#define ZSM_NULL 0x00 /* nothing special */
+/* Buffer and External Status (RR0). */
+#define BES_BRK 0x80 /* Break (Abort). */
+#define BES_TXU 0x40 /* Tx Underrun (EOM). */
+#define BES_CTS 0x20 /* CTS. */
+#define BES_SYNC 0x10 /* Sync. */
+#define BES_DCD 0x08 /* DCD. */
+#define BES_TXE 0x04 /* Tx Empty. */
+#define BES_ZC 0x02 /* Zero Count. */
+#define BES_RXA 0x01 /* Rx Available. */
-#define ZSM_RESET_IUS 0x38 /* reset interrupt under service */
-#define ZSM_RESET_ERR 0x30 /* reset error cond */
-#define ZSM_RESET_TXINT 0x28 /* reset xmit interrupt pending */
-#define ZSM_EI_NEXTRXC 0x20 /* enable int. on next rcvd char */
-#define ZSM_SEND_ABORT 0x18 /* send abort (SDLC) */
-#define ZSM_RESET_STINT 0x10 /* reset external/status interrupt */
-#define ZSM_POINTHIGH 0x08 /* `point high' (use r8-r15) */
-#define ZSM_NULL 0x00 /* nothing special */
+/* Clock Mode Control (WR11). */
+#define CMC_XTAL 0x80 /* -RTxC connects to quartz crystal. */
+#define CMC_RC_DPLL 0x60 /* Rx Clock from DPLL. */
+#define CMC_RC_BRG 0x40 /* Rx Clock from BRG. */
+#define CMC_RC_TRXC 0x20 /* Rx Clock from -TRxC. */
+#define CMC_RC_RTXC 0x00 /* Rx Clock from -RTxC. */
+#define CMC_TC_DPLL 0x18 /* Tx Clock from DPLL */
+#define CMC_TC_BRG 0x10 /* Tx Clock from BRG */
+#define CMC_TC_TRXC 0x08 /* Tx Clock from -TRxC. */
+#define CMC_TC_RTXC 0x00 /* Tx Clock from -RTxC. */
+#define CMC_TRXC_OUT 0x04 /* -TRxC is output. */
+#define CMC_TRXC_DPLL 0x03 /* -TRxC from DPLL */
+#define CMC_TRXC_BRG 0x02 /* -TRxC from BRG */
+#define CMC_TRXC_XMIT 0x01 /* -TRxC from Tx clock. */
+#define CMC_TRXC_XTAL 0x00 /* -TRxC from XTAL. */
-/*
- * Commands for Write Register 0 (`Command Register').
- * These are just the command modifiers or'ed with register number 0
- * (which of course equals the command modifier).
- */
-#define WR0_RESET_EOM ZSM_RESET_TXUEOM
-#define WR0_RESET_TXCRC ZSM_RESET_TXCRC
-#define WR0_RESET_RXCRC ZSM_RESET_RXCRC
-#define WR0_CLR_INTR ZSM_RESET_IUS
-#define WR0_RESET_ERRORS ZSM_RESET_ERR
-#define WR0_EI_NEXTRXC ZSM_EI_NEXTRXC
-#define WR0_SEND_ABORT ZSM_SEND_ABORT
-#define WR0_RESET_STATUS ZSM_RESET_STINT
-#define WR0_RESET_TXINT ZSM_RESET_TXINT
+/* Miscellaneous Control Bits part 1 (WR10). */
+#define MCB1_CRC1 0x80 /* CRC presets to 1. */
+#define MCB1_FM0 0x60 /* FM0 Encoding. */
+#define MCB1_FM1 0x40 /* FM1 Encoding. */
+#define MCB1_NRZI 0x20 /* NRZI Encoding. */
+#define MCB1_NRZ 0x00 /* NRZ Encoding. */
+#define MCB1_AOP 0x10 /* Active On Poll. */
+#define MCB1_MI 0x08 /* Mark Idle. */
+#define MCB1_AOU 0x04 /* Abort On Underrun. */
+#define MCB1_LM 0x02 /* Loop Mode. */
+#define MCB1_SIX 0x01 /* 6 or 12 bit SYNC. */
-/*
- * Bits in Write Register 1 (`Transmit/Receive Interrupt and Data
- * Transfer Mode Definition'). Note that bits 3 and 4 are taken together
- * as a single unit, and bits 5 and 6 are useful only if bit 7 is set.
- */
-#define WR1_REQ_WAIT 0x80 /* WAIT*-REQ* pin gives WAIT* */
-#define WR1_REQ_REQ 0xc0 /* WAIT*-REQ* pin gives REQ* */
-#define WR1_REQ_TX 0x00 /* WAIT*-REQ* pin follows xmit buf */
-#define WR1_REQ_RX 0x20 /* WAIT*-REQ* pin follows recv buf */
+/* Miscellaneous Control Bits part 2 (WR14). */
+#define MCB2_NRZI 0xe0 /* DPLL - NRZI mode. */
+#define MCB2_FM 0xc0 /* DPLL - FM mode. */
+#define MCB2_RTXC 0xa0 /* DPLL - Clock from -RTxC. */
+#define MCB2_BRG 0x80 /* DPLL - Clock from BRG. */
+#define MCB2_OFF 0x60 /* DPLL - Disable. */
+#define MCB2_RMC 0x40 /* DPLL - Reset Missing Clock. */
+#define MCB2_ESM 0x20 /* DPLL - Enter Search Mode. */
+#define MCB2_LL 0x10 /* Local Loopback. */
+#define MCB2_AE 0x08 /* Auto Echo. */
+#define MCB2_REQ 0x04 /* Request Function. */
+#define MCB2_PCLK 0x02 /* BRG source is PCLK. */
+#define MCB2_BRGE 0x01 /* BRG enable. */
-#define WR1_RIE_NONE 0x00 /* disable rxint entirely */
-#define WR1_RIE_FIRST 0x08 /* rxint on first char & on S.C. */
-#define WR1_RIE 0x10 /* rxint per char & on S.C. */
-#define WR1_RIE_SPECIAL_ONLY 0x18 /* rxint on S.C. only */
+/* Master Interrupt Control (WR9). */
+#define MIC_FHR 0xc0 /* Force Hardware Reset. */
+#define MIC_CRA 0x80 /* Channel Reset A. */
+#define MIC_CRB 0x40 /* Channel Reset B. */
+#define MIC_SIE 0x20 /* Software INTACK Enable. */
+#define MIC_SH 0x10 /* Status High. */
+#define MIC_MIE 0x08 /* Master Interrupt Enable. */
+#define MIC_DLC 0x04 /* Disable Lower Chain. */
+#define MIC_NV 0x02 /* No Vector. */
+#define MIC_VIS 0x01 /* Vector Includes Status. */
-#define WR1_PE_SC 0x04 /* parity error is special condition */
-#define WR1_TIE 0x02 /* transmit interrupt enable */
-#define WR1_SIE 0x01 /* external/status interrupt enable */
+/* Transmit/Receive Miscellaneous Parameters and Modes. */
+#define MPM_CM64 0xc0 /* X64 Clock Mode. */
+#define MPM_CM32 0x80 /* X32 Clock Mode. */
+#define MPM_CM16 0x40 /* X16 Clock Mode. */
+#define MPM_CM1 0x00 /* X1 Clock Mode. */
+#define MPM_EXT 0x30 /* External Sync Mode. */
+#define MPM_SDLC 0x20 /* SDLC mode. */
+#define MPM_BI 0x10 /* 16-bit Sync (bi-sync). */
+#define MPM_MONO 0x00 /* 8-bit Sync (mono-sync). */
+#define MPM_SB2 0x0c /* Async mode: 2 stopbits. */
+#define MPM_SB15 0x08 /* Async mode: 1.5 stopbits. */
+#define MPM_SB1 0x04 /* Async mode: 1 stopbit. */
+#define MPM_SYNC 0x00 /* Sync Mode Enable. */
+#define MPM_EVEN 0x02 /* Async mode: even parity. */
+#define MPM_PE 0x01 /* Async mode: parity enable. */
-#define WR1_IMASK 0x1F /* mask of all itr. enable bits. */
+/* Receive Parameters and Control (WR3). */
+#define RPC_RB8 0xc0 /* 8 databits. */
+#define RPC_RB6 0x80 /* 6 databits. */
+#define RPC_RB7 0x40 /* 7 databits. */
+#define RPC_RB5 0x00 /* 5 databits. */
+#define RPC_AE 0x20 /* Auto Enable. */
+#define RPC_EHM 0x10 /* Enter Hunt Mode. */
+#define RPC_CRC 0x08 /* CRC Enable. */
+#define RPC_ASM 0x04 /* Address Search Mode. */
+#define RPC_LI 0x02 /* SYNC Character Load Inhibit */
+#define RPC_RXE 0x01 /* Receiver Enable */
-/* HSIS compat */
-#define WR1_REQ_ENABLE (WR1_REQ_WAIT | WR1_REQ_TX)
+/* Transmit Parameter and Control (WR5). */
+#define TPC_DTR 0x80 /* DTR. */
+#define TPC_TB8 0x60 /* 8 databits. */
+#define TPC_TB6 0x40 /* 6 databits. */
+#define TPC_TB7 0x20 /* 7 databits. */
+#define TPC_TB5 0x00 /* 5 or fewer databits. */
+#define TPC_SB 0x10 /* Send break. */
+#define TPC_TXE 0x08 /* Transmitter Enable. */
+#define TPC_CRC16 0x04 /* CRC16. */
+#define TPC_RTS 0x02 /* RTS. */
+#define TPC_CRC 0x01 /* CRC Enable. */
-/*
- * Bits in Write Register 3 (`Receive Parameters and Control').
- * Bits 7 and 6 are taken as a unit. Note that the receive bits
- * per character ordering is insane.
- *
- * Here `hardware flow control' means CTS enables the transmitter
- * and DCD enables the receiver. The latter is neither interesting
- * nor useful, and gets in our way, making it almost unusable.
- */
-#define WR3_RX_5 0x00 /* receive 5 bits per char */
-#define WR3_RX_7 0x40 /* receive 7 bits per char */
-#define WR3_RX_6 0x80 /* receive 6 bits per char */
-#define WR3_RX_8 0xc0 /* receive 8 bits per char */
-#define WR3_RXSIZE 0xc0 /* receive char size mask */
-
-#define WR3_HFC 0x20 /* hardware flow control */
-#define WR3_HUNT 0x10 /* enter hunt mode */
-#define WR3_RXCRC_ENABLE 0x08 /* enable recv crc calculation */
-#define WR3_ADDR_SEARCH_MODE 0x04 /* address search mode (SDLC only) */
-#define WR3_SDLC_SHORT_ADDR 0x02 /* short address mode (SDLC only) */
-#define WR3_SYNC_LOAD_INH 0x02 /* sync character load inhibit */
-#define WR3_RX_ENABLE 0x01 /* receiver enable */
-
-/*
- * Bits in Write Register 4 (`Transmit/Receive Miscellaneous Parameters
- * and Modes'). Bits 7&6, 5&4, and 3&2 are taken as units.
- */
-#define WR4_CLK_X1 0x00 /* clock divisor = 1 */
-#define WR4_CLK_X16 0x40 /* clock divisor = 16 */
-#define WR4_CLK_X32 0x80 /* clock divisor = 32 */
-#define WR4_CLK_X64 0xc0 /* clock divisor = 64 */
-#define WR4_CLK_MASK 0xc0 /* clock divisor mask */
-
-#define WR4_MONOSYNC 0x00 /* 8 bit sync char (sync only) */
-#define WR4_BISYNC 0x10 /* 16 bit sync char (sync only) */
-#define WR4_SDLC 0x20 /* SDLC mode */
-#define WR4_EXTSYNC 0x30 /* external sync mode */
-#define WR4_SYNC_MASK 0x30 /* sync mode bit mask */
-
-#define WR4_SYNCMODE 0x00 /* no stop bit (sync mode only) */
-#define WR4_ONESB 0x04 /* 1 stop bit */
-#define WR4_1P5SB 0x08 /* 1.5 stop bits (clk cannot be 1x) */
-#define WR4_TWOSB 0x0c /* 2 stop bits */
-#define WR4_SBMASK 0x0c /* mask of all stop bits */
-
-#define WR4_EVENP 0x02 /* check for even parity */
-#define WR4_PARENB 0x01 /* enable parity checking */
-#define WR4_PARMASK 0x03 /* mask of all parity bits */
-
-/*
- * Bits in Write Register 5 (`Transmit Parameter and Controls').
- * Bits 6 and 5 are taken as a unit; the ordering is, as with RX
- * bits per char, not sensible.
- */
-#define WR5_DTR 0x80 /* assert (set to -12V) DTR */
-
-#define WR5_TX_5 0x00 /* transmit 5 or fewer bits */
-#define WR5_TX_7 0x20 /* transmit 7 bits */
-#define WR5_TX_6 0x40 /* transmit 6 bits */
-#define WR5_TX_8 0x60 /* transmit 8 bits */
-#define WR5_TXSIZE 0x60 /* transmit char size mask */
-
-#define WR5_BREAK 0x10 /* send break (continuous 0s) */
-#define WR5_TX_ENABLE 0x08 /* enable transmitter */
-#define WR5_CRC16 0x04 /* use CRC16 (off => use SDLC) */
-#define WR5_RTS 0x02 /* assert RTS */
-#define WR5_TXCRC_ENABLE 0x01 /* enable xmit crc calculation */
-
-#ifdef not_done_here
-/*
- * Bits in Write Register 7 when the chip is in SDLC mode.
- */
-#define WR7_SDLCFLAG 0x7e /* this value makes SDLC mode work */
-#endif
-
-/*
- * Bits in Write Register 7' (WR_ENHANCED above). This register is
- * only available on the 85230. Dispite the fact it contains flags
- * and not a single value, the register was named as it is read
- * via RR14. Weird.
- */
- /* 0x80 unused */
-#define WR7P_EXTEND_READ 0x40 /* modify read map; make most regs readable */
-#define WR7P_TX_FIFO 0x20 /* change level for Tx FIFO empty int */
-#define WR7P_DTR_TIME 0x10 /* modifies deact. speed of /DTR//REQ */
-#define WR7P_RX_FIFO 0x08 /* Rx FIFO int on 1/2 full? */
-#define WR7P_RTS_DEACT 0x04 /* automatically deassert RTS */
-#define WR7P_AUTO_EOM_RESET 0x02 /* automatically reset EMO/Tx Underrun */
-#define WR7P_AUTO_TX_FLAG 0x01 /* Auto send SDLC flag at transmit start */
-
-/*
- * Bits in Write Register 9 (`Master Interrupt Control'). Bits 7 & 6
- * are taken as a unit and indicate the type of reset; 00 means no reset
- * (and is not defined here).
- */
-#define WR9_HARD_RESET 0xc0 /* force hardware reset */
-#define WR9_A_RESET 0x80 /* reset channel A (0) */
-#define WR9_B_RESET 0x40 /* reset channel B (1) */
-#define WR9_SOFT_INTAC 0x20 /* Not in NMOS version */
-
-#define WR9_STATUS_HIGH 0x10 /* status in high bits of intr vec */
-#define WR9_MASTER_IE 0x08 /* master interrupt enable */
-#define WR9_DLC 0x04 /* disable lower chain */
-#define WR9_NO_VECTOR 0x02 /* no vector */
-#define WR9_VECTOR_INCL_STAT 0x01 /* vector includes status */
-
-/*
- * Bits in Write Register 10 (`Miscellaneous Transmitter/Receiver Control
- * Bits'). Bits 6 & 5 are taken as a unit, and some of the bits are
- * meaningful only in certain modes. Bleah.
- */
-#define WR10_PRESET_ONES 0x80 /* preset CRC to all 1 (else all 0) */
-
-#define WR10_NRZ 0x00 /* NRZ encoding */
-#define WR10_NRZI 0x20 /* NRZI encoding */
-#define WR10_FM1 0x40 /* FM1 encoding */
-#define WR10_FM0 0x60 /* FM0 encoding */
-
-#define WR10_GA_ON_POLL 0x10 /* go active on poll (loop mode) */
-#define WR10_MARK_IDLE 0x08 /* all 1s (vs flag) when idle (SDLC) */
-#define WR10_ABORT_ON_UNDERRUN 0x04 /* abort on xmit underrun (SDLC) */
-#define WR10_LOOP_MODE 0x02 /* loop mode (SDLC) */
-#define WR10_6_BIT_SYNC 0x01 /* 6 bits per sync char (sync modes) */
-
-/*
- * Bits in Write Register 11 (`Clock Mode Control'). Bits 6&5, 4&3, and
- * 1&0 are taken as units. Various bits depend on other bits in complex
- * ways; see the Zilog manual.
- */
-#define WR11_XTAL 0x80 /* have xtal between RTxC* and SYNC* */
- /* (else have TTL oscil. on RTxC*) */
-#define WR11_RXCLK_RTXC 0x00 /* recv clock taken from RTxC* pin */
-#define WR11_RXCLK_TRXC 0x20 /* recv clock taken from TRxC* pin */
-#define WR11_RXCLK_BAUD 0x40 /* recv clock taken from BRG */
-#define WR11_RXCLK_DPLL 0x60 /* recv clock taken from DPLL */
-
-#define WR11_TXCLK_RTXC 0x00 /* xmit clock taken from RTxC* pin */
-#define WR11_TXCLK_TRXC 0x08 /* xmit clock taken from TRxC* pin */
-#define WR11_TXCLK_BAUD 0x10 /* xmit clock taken from BRG */
-#define WR11_TXCLK_DPLL 0x18 /* xmit clock taken from DPLL */
-
-#define WR11_TRXC_OUT_ENA 0x04 /* TRxC* pin will be an output */
- /* (unless it is being used above) */
-#define WR11_TRXC_XTAL 0x00 /* TRxC output from xtal oscillator */
-#define WR11_TRXC_XMIT 0x01 /* TRxC output from xmit clock */
-#define WR11_TRXC_BAUD 0x02 /* TRxC output from BRG */
-#define WR11_TRXC_DPLL 0x03 /* TRxC output from DPLL */
-
-/*
- * Formula for Write Registers 12 and 13 (`Lower Byte of Baud Rate
- * Generator Time Constant' and `Upper Byte of ...'). Inputs:
- *
- * f BRG input clock frequency (in Hz) AFTER division
- * by 1, 16, 32, or 64 (per clock divisor in WR4)
- * bps desired rate in bits per second (9600, etc)
- *
- * We want
- *
- * f
- * ----- + 0.5 - 2
- * 2 bps
- *
- * rounded down to an integer. This can be computed entirely
- * in integer arithemtic as:
- *
- * f + bps
- * ------- - 2
- * 2 bps
- */
-#define BPS_TO_TCONST(f, bps) ((((f) + (bps)) / (2 * (bps))) - 2)
-
-/* inverse of above: given a BRG Time Constant, return Bits Per Second */
-#define TCONST_TO_BPS(f, tc) ((f) / 2 / ((tc) + 2))
-
-/*
- * Bits in Write Register 14 (`Miscellaneous Control Bits').
- * Bits 7 through 5 are taken as a unit and make up a `DPLL command'.
- */
-#define WR14_DPLL_NOOP 0x00 /* leave DPLL alone */
-#define WR14_DPLL_SEARCH 0x20 /* enter search mode */
-#define WR14_DPLL_RESET_CM 0x40 /* reset `clock missing' in RR10 */
-#define WR14_DPLL_DISABLE 0x60 /* disable DPLL (continuous search) */
-#define WR14_DPLL_SRC_BAUD 0x80 /* set DPLL src = BRG */
-#define WR14_DPLL_SRC_RTXC 0xa0 /* set DPLL src = RTxC* or xtal osc */
-#define WR14_DPLL_FM 0xc0 /* operate in FM mode */
-#define WR14_DPLL_NRZI 0xe0 /* operate in NRZI mode */
-
-#define WR14_LOCAL_LOOPBACK 0x10 /* set local loopback mode */
-#define WR14_AUTO_ECHO 0x08 /* set auto echo mode */
-#define WR14_DTR_REQ 0x04 /* DTR* / REQ* pin gives REQ* */
-#define WR14_BAUD_FROM_PCLK 0x02 /* BRG clock taken from PCLK */
- /* (else from RTxC* pin or xtal osc) */
-#define WR14_BAUD_ENA 0x01 /* enable BRG countdown */
-
-/*
- * Bits in Write Register 15 (`External/Status Interrupt Control').
- * Most of these cause status interrupts whenever the corresponding
- * bit or pin changes state (i.e., any rising or falling edge).
- *
- * NOTE: WR15_SDLC_FIFO & WR15_ENABLE_ENHANCED should not be
- * set on an NMOS 8530. Also, WR15_ENABLE_ENHANCED is only
- * available on the 85230.
- */
-#define WR15_BREAK_IE 0x80 /* enable break/abort status int */
-#define WR15_TXUEOM_IE 0x40 /* enable TX underrun/EOM status int */
-#define WR15_CTS_IE 0x20 /* enable CTS* pin status int */
-#define WR15_SYNCHUNT_IE 0x10 /* enable SYNC* pin/hunt status int */
-#define WR15_DCD_IE 0x08 /* enable DCD* pin status int */
-#define WR15_SDLC_FIFO 0x04 /* enable SDLC FIFO enhancements */
-#define WR15_ZERO_COUNT_IE 0x02 /* enable BRG-counter = 0 status int */
-#define WR15_ENABLE_ENHANCED 0x01 /* enable writing WR7' at reg 7 */
-
-/*
- * Bits in Read Register 0 (`Transmit/Receive Buffer Status and External
- * Status').
- */
-#define RR0_BREAK 0x80 /* break/abort detected */
-#define RR0_TXUNDER 0x40 /* transmit underrun/EOM (sync) */
-#define RR0_CTS 0x20 /* clear to send */
-#define RR0_SYNC_HUNT 0x10 /* sync/hunt (sync mode) */
-#define RR0_DCD 0x08 /* data carrier detect */
-#define RR0_TX_READY 0x04 /* transmit buffer empty */
-#define RR0_ZERO_COUNT 0x02 /* zero count in baud clock */
-#define RR0_RX_READY 0x01 /* received character ready */
-
-/*
- * Bits in Read Register 1 (the Zilog book does not name this one).
- */
-#define RR1_EOF 0x80 /* end of frame (SDLC mode) */
-#define RR1_FE 0x40 /* CRC/framing error */
-#define RR1_DO 0x20 /* data (receiver) overrun */
-#define RR1_PE 0x10 /* parity error */
-#define RR1_RC0 0x08 /* residue code 0 (SDLC mode) */
-#define RR1_RC1 0x04 /* residue code 1 (SDLC mode) */
-#define RR1_RC2 0x02 /* residue code 2 (SDLC mode) */
-#define RR1_ALL_SENT 0x01 /* all chars out of xmitter (async) */
-
-/*
- * Read Register 2 in B channel contains status bits if VECTOR_INCL_STAT
- * is set.
- */
-
-/*
- * Bits in Read Register 3 (`Interrupt Pending'). Only channel A
- * has an RR3.
- */
- /* 0x80 unused, returned as 0 */
- /* 0x40 unused, returned as 0 */
-#define RR3_IP_A_RX 0x20 /* channel A recv int pending */
-#define RR3_IP_A_TX 0x10 /* channel A xmit int pending */
-#define RR3_IP_A_STAT 0x08 /* channel A status int pending */
-#define RR3_IP_B_RX 0x04 /* channel B recv int pending */
-#define RR3_IP_B_TX 0x02 /* channel B xmit int pending */
-#define RR3_IP_B_STAT 0x01 /* channel B status int pending */
-
-/*
- * Bits in Read Register 10 (`contains some miscellaneous status bits').
- */
-#define RR10_1_CLOCK_MISSING 0x80 /* 1 clock edge missing (FM mode) */
-#define RR10_2_CLOCKS_MISSING 0x40 /* 2 clock edges missing (FM mode) */
- /* 0x20 unused */
-#define RR10_LOOP_SENDING 0x10 /* xmitter controls loop (SDLC loop) */
- /* 0x08 unused */
- /* 0x04 unused */
-#define RR10_ON_LOOP 0x02 /* SCC is on loop (SDLC/X.21 modes) */
-
-/*
- * Bits in Read Register 15. This register is one of the few that
- * simply reads back the corresponding Write Register.
- */
-#define RR15_BREAK_IE 0x80 /* break/abort status int enable */
-#define RR15_TXUEOM_IE 0x40 /* TX underrun/EOM status int enable */
-#define RR15_CTS_IE 0x20 /* CTS* pin status int enable */
-#define RR15_SYNCHUNT_IE 0x10 /* SYNC* pin/hunt status int enable */
-#define RR15_DCD_IE 0x08 /* DCD* pin status int enable */
- /* 0x04 unused, returned as zero */
-#define RR15_ZERO_COUNT_IE 0x02 /* BRG-counter = 0 status int enable */
- /* 0x01 unused, returned as zero */
+#endif /* _DEV_UART_DEV_Z8530_H_ */
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