PERFORCE change 37045 for review
Marcel Moolenaar
marcel at FreeBSD.org
Wed Aug 27 16:28:26 PDT 2003
http://perforce.freebsd.org/chv.cgi?CH=37045
Change 37045 by marcel at marcel_nfs on 2003/08/27 16:28:17
Add register constants for the enhanced feature register. We
need that later on when we add hardware flow control. Rename
some constants to be more consistent.
While here: always make the size of the Tx FIFO 16 bytes, even
if the Rx FIFO is larger. We don't program the Tx trigger level
so we get interrupts every 16 bytes. However, we assume that all
data has been sent when we get the interrupt. This does not hold
if we previously wrote 32 (or so) characters to the Tx FIFO.
This needs to be improved, but now at least it's correct.
Affected files ...
.. //depot/projects/uart/dev/uart/uart_dev_ns8250.c#22 edit
.. //depot/projects/uart/dev/uart/uart_dev_ns8250.h#2 edit
Differences ...
==== //depot/projects/uart/dev/uart/uart_dev_ns8250.c#22 (text+ko) ====
@@ -277,7 +277,7 @@
uart_barrier(bas);
/* Set RTS & DTR. */
- uart_setreg(bas, REG_MCR, MCR_IENABLE | MCR_RTS | MCR_DTR);
+ uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
uart_barrier(bas);
ns8250_clrint(bas);
@@ -288,7 +288,7 @@
{
/* Clear RTS & DTR. */
- uart_setreg(bas, REG_MCR, MCR_IENABLE);
+ uart_setreg(bas, REG_MCR, MCR_IE);
uart_barrier(bas);
}
@@ -506,7 +506,7 @@
if (error)
return (error);
- mcr = MCR_IENABLE;
+ mcr = MCR_IE;
if (sc->sc_sysdev == NULL) {
/* By using ns8250_init() we also set DTR and RTS. */
ns8250_init(bas, 9600, 8, 1, UART_PARITY_NONE);
@@ -521,8 +521,7 @@
* Set loopback mode. This avoids having garbage on the wire and
* also allows us send and receive data. We set DTR and RTS to
* avoid the possibility that automatic flow-control prevents
- * any data from being sent. We clear IENABLE to avoid raising
- * interrupts.
+ * any data from being sent. We clear IE to avoid raising interrupts.
*/
uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_DTR | MCR_RTS);
uart_barrier(bas);
@@ -547,7 +546,7 @@
return (0);
}
- uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_DMA_MODE | FCR_RX_HIGH |
+ uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_DMA | FCR_RX_HIGH |
FCR_XMT_RST | FCR_RCV_RST);
uart_barrier(bas);
@@ -616,7 +615,12 @@
"Non-standard ns8250 class UART with FIFOs");
}
- sc->sc_txfifosz = sc->sc_rxfifosz;
+ /*
+ * Force the Tx FIFO size to 16 bytes for now. We don't program the
+ * Tx trigger. Also, we assume that all data has been sent when the
+ * interrupt happens.
+ */
+ sc->sc_txfifosz = 16;
return (0);
}
==== //depot/projects/uart/dev/uart/uart_dev_ns8250.h#2 (text+ko) ====
@@ -26,34 +26,59 @@
* $FreeBSD$
*/
-#ifndef _DEV_UART_8250REG_H_
-#define _DEV_UART_8250REG_H_
+#ifndef _DEV_UART_DEV_NS8250_H_
+#define _DEV_UART_DEV_NS8250_H_
+
+/* Enhanced Feature Register. */
+#define EFR_CTS 0x80
+#define EFR_RTS 0x40
+#define EFR_SCD 0x20 /* Special Character Detect. */
+#define EFR_EFC 0x10 /* Enhanced Function Control. */
+#define EFR_SFC_MASK 0x0f /* Software Flow Control. */
+#define EFR_SFC_TX12 0x0c /* BIT: Transmit XON1+2/XOFF1+2. */
+#define EFR_SFC_TX1 0x08 /* BIT: Transmit XON1/XOFF1. */
+#define EFR_SFC_TX2 0x04 /* BIT: Transmit XON2/XOFF2. */
+#define EFR_SFC_RX1 0x02 /* BIT: Receive XON1/XOFF1. */
+#define EFR_SFC_RX2 0x01 /* BIT: Receive XON2/XOFF2. */
+#define EFR_SFC_T12R12 0x0f /* VAL: TX 1+2, RX 1+2. */
+#define EFR_SFC_T1R12 0x0b /* VAL: TX 1, RX 1+2. */
+#define EFR_SFC_T2R12 0x07 /* VAL: TX 2, RX 1+2. */
/* FIFO Control Register. */
+#define FCR_RX_HIGH 0xc0
+#define FCR_RX_MEDH 0x80
+#define FCR_RX_MEDL 0x40
+#define FCR_RX_LOW 0x00
+#define FCR_TX_HIGH 0x30
+#define FCR_TX_MEDH 0x20
+#define FCR_TX_LOW 0x10
+#define FCR_TX_MEDL 0x00
+#define FCR_DMA 0x08
+#define FCR_XMT_RST 0x04
+#define FCR_RCV_RST 0x02
#define FCR_ENABLE 0x01
-#define FCR_RCV_RST 0x02
-#define FCR_XMT_RST 0x04
-#define FCR_DMA_MODE 0x08
-#define FCR_RX_LOW 0x00
-#define FCR_RX_MEDL 0x40
-#define FCR_RX_MEDH 0x80
-#define FCR_RX_HIGH 0xc0
/* Interrupt Enable Register. */
+#define IER_CTS 0x80
+#define IER_RTS 0x40
+#define IER_XOFF 0x20
+#define IER_SLEEP 0x10
+#define IER_EMSC 0x08
+#define IER_ERLS 0x04
+#define IER_ETXRDY 0x02
#define IER_ERXRDY 0x01
-#define IER_ETXRDY 0x02
-#define IER_ERLS 0x04
-#define IER_EMSC 0x08
/* Interrupt Identification Register. */
+#define IIR_FIFO_MASK 0xc0
+#define IIR_RTSCTS 0x20
+#define IIR_XOFF 0x10
#define IIR_IMASK 0x0f
#define IIR_RXTOUT 0x0c
#define IIR_RLS 0x06
#define IIR_RXRDY 0x04
#define IIR_TXRDY 0x02
+#define IIR_MLSC 0x00
#define IIR_NOPEND 0x01
-#define IIR_MLSC 0x00
-#define IIR_FIFO_MASK 0xc0
/* Line Control Register. */
#define LCR_DLAB 0x80
@@ -70,7 +95,7 @@
#define LCR_5BITS 0x00
/* Line Status Register. */
-#define LSR_RCV_FIFO 0x80
+#define LSR_DERR 0x80
#define LSR_TEMT 0x40 /* Transmitter Empty. */
#define LSR_THRE 0x20 /* Transmitter Holding Register Empty. */
#define LSR_BI 0x10
@@ -78,13 +103,15 @@
#define LSR_PE 0x04
#define LSR_OE 0x02
#define LSR_RXRDY 0x01
-#define LSR_RCV_MASK 0x1f
/* Modem Control Register. */
-#define MCR_PRESCALE 0x80
+#define MCR_CS 0x80
+#define MCR_IRE 0x40
+#define MCR_ISEL 0x20
#define MCR_LOOPBACK 0x10
-#define MCR_IENABLE 0x08
-#define MCR_DRS 0x04
+#define MCR_IE 0x08
+#define MCR_LBDCD MCR_IE
+#define MCR_LBRI 0x04
#define MCR_RTS 0x02
#define MCR_DTR 0x01
@@ -98,13 +125,10 @@
#define MSR_DDSR 0x02
#define MSR_DCTS 0x01
-/* Register offsets. */
+/* General registers. */
#define REG_DATA 0 /* Data Register. */
#define REG_RBR REG_DATA /* Receiver Buffer Register (R). */
#define REG_THR REG_DATA /* Transmitter Holding Register (W). */
-#define REG_DLBL 0 /* Divisor Latch (LSB). */
-#define REG_DLBH 1 /* Divisor Latch (MSB). */
-#define REG_DL REG_DLBL /* Divisor Latch (16-bit I/O). */
#define REG_IER 1 /* Interrupt Enable Register */
#define REG_IIR 2 /* Interrupt Ident. Register (R). */
#define REG_FCR 2 /* FIFO Control Register (W). */
@@ -114,4 +138,16 @@
#define REG_MSR 6 /* Modem Status Register. */
#define REG_SPR 7 /* Scratch Pad Register. */
-#endif /* _DEV_UART_8250REG_H_ */
+/* Baudrate registers (LCR[7] = 1). */
+#define REG_DLBL 0 /* Divisor Latch (LSB). */
+#define REG_DLBH 1 /* Divisor Latch (MSB). */
+#define REG_DL REG_DLBL /* Divisor Latch (16-bit I/O). */
+
+/* Enhanced registers (LCR = 0xBF). */
+#define REG_EFR 2 /* Enhanced Feature Register. */
+#define REG_XON1 4 /* XON character 1. */
+#define REG_XON2 5 /* XON character 2. */
+#define REG_XOFF1 6 /* XOFF character 1. */
+#define REG_XOFF2 7 /* XOFF character 2. */
+
+#endif /* _DEV_UART_DEV_NS8250_H_ */
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