USB panic on 8.0/arm

[Gavin Atkinson]

On Tue, 12 May 2009, Hans Petter Selasky wrote:
> On Tuesday 12 May 2009, Gavin Atkinson wrote:
>> Hi all,
>>
>> I have an NSLU2, which I am netbooting.  I've been doing most of my work
>> on it with USB removed from the kernel because the old stack would
>> always panic.  I've recently been trying the new USB stack, and have
>> found that it still panics most of the time on boot.  But not all the
>> time.
> In :
>
> src/sys/dev/usb/controller/ohci_pci.c
>
> Can you try to move the pci busmaster enable call further down in the attach
> routine, until the I/O resources are setup, then add before enable busmaster:
>
> #define OBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0,
> (sc)->sc_io_size, \
>                        BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
> #define OWRITE1(sc, r, x) \
> do { OBARR(sc); bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (r),
> (x)); } while (0)
>
>        OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR);     /* Reset HC */
>
> I'm not sure if it helps. It's just a guess.

I'm assuming you meant to use the "OWRITE4" macro rather than OWRITE1 as 
that's what is used when accessing that register everywhere else. 
Assuming that is the case, I'm afraid the patch (below) makes no 
difference.

Any other ideas?

Thanks,

Gavin

Index: src-head/sys/dev/usb/controller/ohci_pci.c
===================================================================
RCS file: /home/ncvs/src/sys/dev/usb/controller/ohci_pci.c,v
retrieving revision 1.5
diff -u -r1.5 ohci_pci.c
--- src-head/sys/dev/usb/controller/ohci_pci.c  6 Apr 2009 00:32:54 -0000       1.5
+++ src-head/sys/dev/usb/controller/ohci_pci.c  12 May 2009 20:24:00 -0000
@@ -205,7 +205,7 @@
         }
         sc->sc_dev = self;

-       pci_enable_busmaster(self);
+/*     pci_enable_busmaster(self); */

         /*
          * Some Sun PCIO-2 USB controllers have their intpin register
@@ -239,6 +239,17 @@
         }
         device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);

+
+#define OBARR(sc) bus_space_barrier((sc)->sc_io_tag, (sc)->sc_io_hdl, 0, (sc)->sc_io_size, \
+                        BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
+#define OWRITE4(sc, r, x) \
+ do { OBARR(sc); bus_space_write_4((sc)->sc_io_tag, (sc)->sc_io_hdl, (r), (x)); } while (0)
+
+        OWRITE4(sc, OHCI_COMMAND_STATUS, OHCI_HCR);     /* Reset HC */
+
+       pci_enable_busmaster(self);
+
+
         /*
          * ohci_pci_match will never return NULL if ohci_pci_probe
          * succeeded