CPU0: local APIC error 0x40 CPU1: local APIC error 0x40

[John Baldwin]

On Tuesday, March 01, 2011 9:32:58 pm Mike Tancsa wrote:
> On 3/1/2011 9:04 PM, Jeremy Chadwick wrote:
> > On Tue, Mar 01, 2011 at 08:50:17PM -0500, Mike Tancsa wrote:
> >> I had a machine deadlock just now and the only thing on the serial
> >> console was
> >>
> >> CPU0: local APIC error 0x40
> >> CPU1: local APIC error 0x40
> > 
> > The error in question I'm not familiar with, but the code in
> > src/sys/x86/x86/local_apic.c indicates that 0x40 is the contents of the
> > LAPIC ESR (error status register).
> > 
> > Please provide full output from a verbose boot.
> 
> 
> Attached as a .txt file

Hmm, the interrupt pins on the each lapic look fine (they all either have a 
legal vector, are using NMI delivery, or are masked).

All of the places that send IPIs have the interrupt vectors hard-coded as 
constant values in the code.

Unfortunately there is no register that tells us which illegal vector was 
posted.

Were you doing anything related to changing the state of device interrupts 
(cpuset -x, kldload, kldunload, etc.) when this happened?

-- 
John Baldwin