8-STABLE interrupt storm on atapci(?), Dell Inspiron 580

Pyun YongHyeon pyunyh at gmail.com
Fri Mar 12 20:02:29 UTC 2010


On Fri, Mar 12, 2010 at 08:45:24PM +0100, Pierre Beyssac wrote:
> On Fri, Mar 12, 2010 at 11:21:44AM -0800, Pyun YongHyeon wrote:
> > No, it seems there is other issue in brgphy(4). I noticed brgphy(4)
> > blindly try to set jumbo frame related registers. I guess the PHY
> > may not have the register. Back out previous patch and try this
> > one.
> 
> Thanks, works better (the error message is gone), but still negotiates
> at 10baseT/UTP fdx... See attached dmesg.out.

Hmm, try this one and let me know it make any differences.
-------------- next part --------------
Index: sys/dev/mii/miidevs
===================================================================
--- sys/dev/mii/miidevs	(revision 205052)
+++ sys/dev/mii/miidevs	(working copy)
@@ -81,6 +81,7 @@
 oui xxALTIMA			0x000895	Altima Communications
 oui xxBROADCOM			0x000818	Broadcom Corporation
 oui xxBROADCOM_ALT1		0x0050ef	Broadcom Corporation
+oui xxBROADCOM_ALT2		0x00d897	Broadcom Corporation
 oui xxICS			0x00057d	Integrated Circuit Systems
 oui xxSEEQ			0x0005be	Seeq
 oui xxSIS			0x000760	Silicon Integrated Systems
@@ -150,6 +151,7 @@
 model xxBROADCOM_ALT1 BCM5784	0x003a BCM5784 10/100/1000baseTX PHY
 model xxBROADCOM_ALT1 BCM5709C	0x003c BCM5709C 10/100/1000baseTX PHY
 model xxBROADCOM_ALT1 BCM5761	0x003d BCM5761 10/100/1000baseTX PHY
+model xxBROADCOM_ALT2 BCM57780	0x0019 BCM57780 10/100/1000baseTX PHY
 model BROADCOM2 BCM5906		0x0004 BCM5906 10/100baseTX PHY
 
 /* Cicada Semiconductor PHYs (now owned by Vitesse?) */
Index: sys/dev/mii/brgphy.c
===================================================================
--- sys/dev/mii/brgphy.c	(revision 205052)
+++ sys/dev/mii/brgphy.c	(working copy)
@@ -139,6 +139,7 @@
 	MII_PHY_DESC(xxBROADCOM_ALT1, BCM5784),
 	MII_PHY_DESC(xxBROADCOM_ALT1, BCM5709C),
 	MII_PHY_DESC(xxBROADCOM_ALT1, BCM5761),
+	MII_PHY_DESC(xxBROADCOM_ALT2, BCM57780),
 	MII_PHY_DESC(BROADCOM2, BCM5906),
 	MII_PHY_END
 };
@@ -213,6 +214,7 @@
 	switch (bsc->mii_oui) {
 	case MII_OUI_BROADCOM:
 	case MII_OUI_BROADCOM2:
+	case MII_OUI_xxBROADCOM_ALT2:
 		break;
 	case MII_OUI_xxBROADCOM:
 		switch (bsc->mii_model) {
@@ -678,16 +680,18 @@
 brgphy_mii_phy_auto(struct mii_softc *sc)
 {
 	struct brgphy_softc *bsc = (struct brgphy_softc *)sc;
+	uint16_t anar;
 	int ktcr = 0;
 
 	brgphy_reset(sc);
 
 	/* Enable flow control in the advertisement register. */
 	if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
+		anar = PHY_READ(sc, BRGPHY_MII_ANAR) & BRGPHY_ANAR_NP;
 		/* Pause capability advertisement (pause capable & asymmetric) */
 		PHY_WRITE(sc, BRGPHY_MII_ANAR,
 	    	BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA |
-	    	BRGPHY_ANAR_ASP | BRGPHY_ANAR_PC);
+	    	BRGPHY_ANAR_ASP | BRGPHY_ANAR_PC | anar);
 	} else {
 		PHY_WRITE(sc, BRGPHY_SERDES_ANAR, BRGPHY_SERDES_ANAR_FDX |
 			BRGPHY_SERDES_ANAR_HDX | BRGPHY_SERDES_ANAR_BOTH_PAUSE);
@@ -1021,7 +1025,8 @@
 		if (bge_sc->bge_flags & BGE_FLAG_JITTER_BUG)
 			brgphy_fixup_jitter_bug(sc);
 
-		brgphy_jumbo_settings(sc, ifp->if_mtu);
+		if (bge_sc->bge_flags & BGE_FLAG_JUMBO)
+			brgphy_jumbo_settings(sc, ifp->if_mtu);
 
 		if (bge_sc->bge_flags & BGE_FLAG_WIRESPEED)
 			brgphy_ethernet_wirespeed(sc);


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