8.1-PRERELEASE: CPU packages not detected correctly

[Oliver Fromme]

David Xu wrote:
 > Do you have patch for i386 branch ? I want to test.
 > On my Pentium-D machine:
 > 
 > $ sysctl kern.sched.topology_spec
 > kern.sched.topology_spec: <groups>
 >   <group level="1" cache-level="0">
 >    <cpu count="2" mask="0x3">0, 1</cpu>
 >    <flags></flags>
 >    <children>
 >     <group level="3" cache-level="2">
 >      <cpu count="2" mask="0x3">0, 1</cpu>
 >      <flags></flags>
 >     </group>
 >    </children>
 >   </group>
 > </groups>
 > 
 > it seems the kernel thinks that the Pentuim-D is sharing L2 cache,
 > but in fact, the design of the Pentium Ds was simply two P4 cores
 > sitting side by side. They do not share anything and they basically work
 > independently.

Same thing on my intel Atom 330 board at home:

<groups>
 <group level="1" cache-level="0">
  <cpu count="4" mask="0xf">0, 1, 2, 3</cpu>
  <flags></flags>
  <children>
   <group level="3" cache-level="2">
    <cpu count="4" mask="0xf">0, 1, 2, 3</cpu>
    <flags></flags>
    <children>
     <group level="5" cache-level="1">
      <cpu count="2" mask="0x3">0, 1</cpu>
      <flags><flag name="HTT">HTT group</flag>
</flags>
     </group>
     <group level="5" cache-level="1">
      <cpu count="2" mask="0xc">2, 3</cpu>
      <flags><flag name="HTT">HTT group</flag>
</flags>
     </group>
    </children>
   </group>
  </children>
 </group>
</groups>

The intel Atom 330 consists of two "Diamondville" dies on
one package, each with its own 512 KB of L2 cache.  There
is no L3 cache, or any other shared cache.

(Or maybe I misinterpret the XML output; I think that the
"level" and "cache-level" numbers are confusing.)

BTW, I noticed that the indentation problem (newline before
"</flags>") is already fixed in -current, 5 weeks ago.
Any plan to MFC this?

Best regards
   Oliver

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leads to lotsa neat pointer tricks; APL mistakes everything for an
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period, making each line a joyous adventure <wink>.
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