8.1-PRERELEASE: CPU packages not detected correctly

Andriy Gapon avg at icyb.net.ua
Fri Aug 20 06:25:41 UTC 2010


on 19/08/2010 22:15 pluknet said the following:
> On 19 August 2010 21:27, Andriy Gapon <avg at icyb.net.ua> wrote:
>> on 19/08/2010 19:56 pluknet said the following:
>>> CPU: Intel(R) Xeon(R) CPU           E5520  @ 2.27GHz (2763.12-MHz 686-class CPU)
>>>   Origin = "GenuineIntel"  Id = 0x106a5  Family = 6  Model = 1a  Stepping = 5
>>>   Features=0x1781fbbf<FPU,VME,DE,PSE,TSC,MSR,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,MMX,FXSR,SSE,SSE2,HTT>
>>>   Features2=0x80982201<SSE3,SSSE3,CX16,SSE4.1,SSE4.2,POPCNT,<b31>>
>>>   TSC: P-state invariant
>>> real memory  = 4194304000 (4000 MB)
>>> avail memory = 3932786688 (3750 MB)
>>> ACPI APIC Table: <Xen HVM>
>>> FreeBSD/SMP: Multiprocessor System Detected: 3 CPUs
>>> FreeBSD/SMP: 0 package(s) x 1 core(s) x 32 HTT threads
>>>  cpu0 (BSP): APIC ID:  0
>>>  cpu1 (AP/HT): APIC ID:  2
>>>  cpu2 (AP/HT): APIC ID:  4
>> Thanks!
>> BTW, what does Intel's code report?
>> Jung-uk's convenience script:
>> http://people.freebsd.org/~jkim/cpu_topology-12212009.sh
>>
> 
>         Software visible enumeration in the system:
> Number of logical processors visible to the OS: 3
> Number of logical processors visible to this process: 3
> Number of processor cores visible to this process: 3
> Number of physical packages visible to this process: 1
> 
>         Hierarchical counts by levels of processor topology:
>  # of cores in package  0 visible to this process: 3 .


So, original Intel code detects the topology correctly.

Jung-uk,
despite what you said in the parallel followup, I think that this demonstrates
that there is a flaw in your patch as compared to the logic in the
Intel-provided code.
FWIW, I was surprised to see a loop in topo_probe_0x4 - I don't see such a loop
in Intel's code.  Also, (level == 1 && cpu_logical == logical * cores)
verification might be a suspect too.  It may be OK for real hardware, but
emulated hardware may stick to minimal compatibility required.

>         Affinity masks per SMT thread, per core, per package:
> Individual:
>         P:0, C:0, T:0 --> 1
> 
> Core-aggregated:
>         P:0, C:0 --> 1
> Individual:
>         P:0, C:1, T:0 --> 2
> 
> Core-aggregated:
>         P:0, C:1 --> 2
> Individual:
>         P:0, C:2, T:0 --> 4
> 
> Core-aggregated:
>         P:0, C:2 --> 4
> 
> Pkg-aggregated:
>         P:0 --> 7
> 
> 
>         APIC ID listings from affinity masks
> OS cpu   0, Affinity mask       01 - apic id 0
> OS cpu   1, Affinity mask       02 - apic id 2
> OS cpu   2, Affinity mask       04 - apic id 4
> 
> 
> Package 0 Cache and Thread details
> L1D is Level 1 Data cache, size(KBytes)= 32,  Cores/cache= 1, Caches/package= 3
> L1I is Level 1 Instruction cache, size(KBytes)= 32,  Cores/cache= 1,
> Caches/package= 3
> L2 is Level 2 Unified cache, size(KBytes)= 256,  Cores/cache= 1,
> Caches/package= 3
> L3 is Level 3 Unified cache, size(KBytes)= 8192,  Cores/cache= 1,
> Caches/package= 3
>       +----+----+----+
> Cache | L1D| L1D| L1D|
> Size  | 32K| 32K| 32K|
> OScpu#|   0|   1|   2|
> Core  |  c0|  c1|  c2|
> AffMsk|   1|   2|   4|
>       +----+----+----+
> 
> Cache | L1I| L1I| L1I|
> Size  | 32K| 32K| 32K|
>       +----+----+----+
> 
> Cache |  L2|  L2|  L2|
> Size  |256K|256K|256K|
>       +----+----+----+
> 
> Cache |  L3|  L3|  L3|
> Size  |  8M|  8M|  8M|
>       +----+----+----+
> 
> Combined socket AffinityMask= 0x7
> 


-- 
Andriy Gapon


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