RELENG_7_1: bce driver change generating too much interrupts ?
Xin LI
delphij at delphij.net
Tue Dec 2 15:27:29 PST 2008
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Hi,
Here is a patch that adjusts parameters of the interrupt handler, which
reduces interrupts. These parameters are obtained from DragonFly, FYI.
Note that this does not restore previous behavior, say, few interrupt if
no traffic. I'm still looking into the real cause.
geoffroy desvernay wrote:
> Xin LI a écrit :
>> Can anyone try reverting the changeset itself? There are two recent
>> changesets:
>>
>> http://www.delphij.net/bce-185161.diff.bz2
>> http://www.delphij.net/bce-184826.diff.bz2
>>
>> You can revert the change by doing this:
>>
>> cd /usr/src
>> fetch http://www.delphij.net/bce-185161.diff.bz2
>> fetch http://www.delphij.net/bce-184826.diff.bz2
>> bzcat bce-185161.diff.bz2 | patch -R
>> bzcat bce-184826.diff.bz2 | patch -R
>>
>> I'll check what's happening ASAP.
>>
> Done:
>
> I'd say it seems to be related...
>
> Before applying your patches:
> # vmstat -i
> interrupt total rate
> irq1: atkbd0 18 0
> irq14: ata0 58 0
> irq20: uhci1 96 0
> irq21: uhci0 uhci+ 5 0
> irq78: mfi0 539747 3
> cpu0: timer 350029937 1999
> irq256: bce0 6757905080 38611
> irq259: bce1 8296789513 47403
> cpu1: timer 350029945 1999
> cpu2: timer 350030010 1999
> cpu3: timer 350030025 1999
> Total 16455354434 94018
>
>
> After patch, make buildkernel && make reinstallkernel and reboot
> interrupt total rate
> irq1: atkbd0 18 0
> irq14: ata0 58 0
> irq20: uhci1 2 0
> irq21: uhci0 uhci+ 5 0
> irq78: mfi0 3947 24
> cpu0: timer 320361 1989
> irq256: bce0 6658 41
> irq259: bce1 1428 8
> cpu1: timer 320320 1989
> cpu2: timer 320380 1989
> cpu3: timer 320507 1990
> Total 1293684 8035
>
- --
Xin LI <delphij at delphij.net> http://www.delphij.net/
FreeBSD - The Power to Serve!
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-------------- next part --------------
--- if_bce.c 2008-12-02 14:02:30.078918595 -0800
+++ .#if_bce.c.1.34.2.3.2.1 2008-12-02 13:49:07.000000000 -0800
@@ -925,15 +925,15 @@
sc->bce_rx_ticks = 0;
#else
/* Improve throughput at the expense of increased latency. */
- sc->bce_tx_quick_cons_trip_int = 20;
- sc->bce_tx_quick_cons_trip = 20;
- sc->bce_tx_ticks_int = 80;
- sc->bce_tx_ticks = 80;
-
- sc->bce_rx_quick_cons_trip_int = 6;
- sc->bce_rx_quick_cons_trip = 6;
- sc->bce_rx_ticks_int = 18;
- sc->bce_rx_ticks = 18;
+ sc->bce_tx_quick_cons_trip_int = 255;
+ sc->bce_tx_quick_cons_trip = 255;
+ sc->bce_tx_ticks_int = 1022;
+ sc->bce_tx_ticks = 1022;
+
+ sc->bce_rx_quick_cons_trip_int = 128;
+ sc->bce_rx_quick_cons_trip = 128;
+ sc->bce_rx_ticks_int = 125;
+ sc->bce_rx_ticks = 125;
#endif
/* Update statistics once every second. */
@@ -2555,7 +2555,7 @@
} else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT)
sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
- if (sc->bce_phy_flags && BCE_PHY_SERDES_FLAG) {
+ if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
sc->bce_flags |= BCE_NO_WOL_FLAG;
if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
sc->bce_phy_addr = 2;
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