ports/148726: [PATCH] cad/p5-Verilog-Perl: [SUMMARIZE CHANGES]

[Otacílio de Araújo Ramos Neto]

>Number:         148726
>Category:       ports
>Synopsis:       [PATCH] cad/p5-Verilog-Perl: [SUMMARIZE CHANGES]
>Confidential:   no
>Severity:       non-critical
>Priority:       low
>Responsible:    freebsd-ports-bugs
>State:          open
>Quarter:        
>Keywords:       
>Date-Required:
>Class:          change-request
>Submitter-Id:   current-users
>Arrival-Date:   Sun Jul 18 03:30:06 UTC 2010
>Closed-Date:
>Last-Modified:
>Originator:     Otacílio de Araújo Ramos Neto
>Release:        FreeBSD 8.0-RELEASE i386
>Organization:
>Environment:
FreeBSD squitch 8.0-RELEASE FreeBSD 8.0-RELEASE #0: Sat Nov 21 15:48:17 UTC 2009     root at almeida.cse.buffalo.edu:/usr/obj/usr/src/sys/GENERIC  i386

>Description:
Upgrade p5-Verilog-Perl to version 3.251
>How-To-Repeat:

>Fix:


Patch attached with submission follows:

===> Generating patch
===> Viewing diff with more
diff -ruN --exclude=CVS /usr/ports/cad/p5-Verilog-Perl.old/Makefile /usr/ports/cad/p5-Verilog-Perl/Makefile
--- /usr/ports/cad/p5-Verilog-Perl.old/Makefile	2010-01-17 21:57:34.000000000 -0300
+++ /usr/ports/cad/p5-Verilog-Perl/Makefile	2010-07-17 23:51:41.386346000 -0300
@@ -2,11 +2,11 @@
 # Date created:		11 Apr 2009
 # Whom:			Otacilio de Araujo Ramos Neto <otacilio.neto at ee.ufcg.edu.br>
 #
-# $FreeBSD: ports/cad/p5-Verilog-Perl/Makefile,v 1.9 2010/01/18 00:57:34 pgollucci Exp $
+# $FreeBSD: ports/cad/p5-Verilog-Perl/Makefile,v 1.7 2009/11/04 15:43:10 miwi Exp $
 #
 
 PORTNAME=	Verilog-Perl
-PORTVERSION=	3.223
+PORTVERSION=	3.251
 CATEGORIES=	cad perl5
 MASTER_SITES=	CPAN
 PKGNAMEPREFIX=	p5-
@@ -28,9 +28,9 @@
 	Verilog::Parser.3 Verilog::Getopt.3 Verilog::Netlist::Module.3 \
 	Verilog::Preproc.3 Verilog::Language.3 Verilog::Netlist::Net.3 \
 	Verilog::SigParser.3 Verilog::Netlist.3 Verilog::Netlist::Pin.3 \
-	Verilog::Netlist::Cell.3 Verilog::Netlist::Port.3 \
+	Verilog::Netlist::Cell.3 Verilog::Netlist::Port.3 Verilog::Netlist::Defparam.3 \
 	Verilog::Netlist::File.3 Verilog::Netlist::Subclass.3 \
-	Verilog::Netlist::ContAssign.3 \
+	Verilog::Netlist::ContAssign.3 Verilog::Netlist::ModPort.3 \
 	Verilog::Verilog-Perl.3 Verilog::Netlist::Interface.3 Verilog::Std.3
 
 .include <bsd.port.pre.mk>
diff -ruN --exclude=CVS /usr/ports/cad/p5-Verilog-Perl.old/distinfo /usr/ports/cad/p5-Verilog-Perl/distinfo
--- /usr/ports/cad/p5-Verilog-Perl.old/distinfo	2010-01-17 21:57:34.000000000 -0300
+++ /usr/ports/cad/p5-Verilog-Perl/distinfo	2010-07-17 22:57:28.020003000 -0300
@@ -1,3 +1,3 @@
-MD5 (Verilog-Perl-3.223.tar.gz) = 54405173d5796dc8dee6a630ae1583c2
-SHA256 (Verilog-Perl-3.223.tar.gz) = 9dc9a42938173580c8cbf5bb46760de53d950f3d2f44ceb3c4d6cad787443df6
-SIZE (Verilog-Perl-3.223.tar.gz) = 212651
+MD5 (Verilog-Perl-3.251.tar.gz) = ff7bbae6e7d2c3e8c8e1f7eee948b08e
+SHA256 (Verilog-Perl-3.251.tar.gz) = ee4742c36f84a6170340a1c79b5e5ebaa230d2fb08f85edde479dfd56cd0b708
+SIZE (Verilog-Perl-3.251.tar.gz) = 232475
diff -ruN --exclude=CVS /usr/ports/cad/p5-Verilog-Perl.old/p5-Verilog-Perl-3.251.patch /usr/ports/cad/p5-Verilog-Perl/p5-Verilog-Perl-3.251.patch
--- /usr/ports/cad/p5-Verilog-Perl.old/p5-Verilog-Perl-3.251.patch	1969-12-31 21:00:00.000000000 -0300
+++ /usr/ports/cad/p5-Verilog-Perl/p5-Verilog-Perl-3.251.patch	2010-07-18 00:20:20.000000000 -0300
@@ -0,0 +1 @@
+===> Generating patch
diff -ruN --exclude=CVS /usr/ports/cad/p5-Verilog-Perl.old/pkg-plist /usr/ports/cad/p5-Verilog-Perl/pkg-plist
--- /usr/ports/cad/p5-Verilog-Perl.old/pkg-plist	2009-11-04 12:43:10.000000000 -0300
+++ /usr/ports/cad/p5-Verilog-Perl/pkg-plist	2010-07-17 23:51:41.386346000 -0300
@@ -7,15 +7,17 @@
 %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Language.pm
 %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist.pm
 %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Cell.pm
+%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/ContAssign.pm
+%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Defparam.pm
 %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/File.pm
 %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Interface.pm
 %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Logger.pm
+%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/ModPort.pm
 %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Module.pm
 %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Net.pm
 %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Pin.pm
 %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Port.pm
 %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/Subclass.pm
-%%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Netlist/ContAssign.pm
 %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Parser.pm
 %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/Preproc.pm
 %%SITE_PERL%%/%%PERL_ARCH%%/Verilog/SigParser.pm
===> Done


>Release-Note:
>Audit-Trail:
>Unformatted: