performance by endian
Mori Hiroki
yamori813 at yahoo.co.jp
Wed Jul 26 02:11:00 UTC 2017
Hi
Sorry I talk about AR9331 soc.
I check boot log.
RT3050 is this.
Cache info:
picache_stride = 4096
picache_loopcount = 8
pdcache_stride = 4096
pdcache_loopcount = 4
cpu0: MIPS Technologies processor v76.150
MMU: Standard TLB, 32 entries (4K 16K 64K 256K 1M 16M 64M 256M pg sizes)
L1 i-cache: 4 ways of 256 sets, 32 bytes per line
L1 d-cache: 4 ways of 128 sets, 32 bytes per line
L2 cache: disabled Config1=0xbea3319e<PerfCount,WatchRegs,MIPS16,EJTAG>
Config2=0x80000000
Config3=0x420
AR9331 is this.
Cache info:
picache_stride = 4096
picache_loopcount = 16
pdcache_stride = 4096
pdcache_loopcount = 8
max line size = 32
cpu0: MIPS Technologies processor v116.147
MMU: Standard TLB, 16 entries (4K 16K 64K 256K 1M 16M 64M 256M pg sizes)
L1 i-cache: 4 ways of 512 sets, 32 bytes per line
L1 d-cache: 4 ways of 256 sets, 32 bytes per line
L2 cache: disabled
Config1=0x9ee3519e<PerfCount,WatchRegs,MIPS16,EJTAG>
Config2=0x80000000
Config3=0x20
Config7=0x0
I seem AR9331 have more cache than RT3050.
awk script is this.
BEGIN {
printf "%d¥n", fib(32)
}
function fib(n) {
if (n < 2) return n
return fib(n - 2) + fib(n - 1)
}
----- Original Message -----
> From: Adrian Chadd <adrian.chadd at gmail.com>
> To: Mori Hiroki <yamori813 at yahoo.co.jp>
> Cc: "freebsd-mips at freebsd.org" <freebsd-mips at freebsd.org>
> Date: 2017/7/26, Wed 02:14
> Subject: Re: performance by endian
>
> well, how much cache, how much out-of-order is it? The AR9330 SoC has
> very limited cache :(
>
>
>
> -adrian
>
>
> On 24 July 2017 at 00:53, Mori Hiroki <yamori813 at yahoo.co.jp> wrote:
>> Hi.
>>
>> I checked fib(32) by awk script.
>>
>> RT3050 is 80 sec
>> AR9330 is 99 sec
>>
>>
>> AR9330 is newer and clock is hight. But slow.
>>
>> Why this result ?
>>
>> I suspect this is endian issue.
>>
>> I have problem mruby performance at Atheros SOC.
>> It is slow almost double from same clock little
>> endian mips soc.
>>
>> Regards
>>
>> Hiroki Mori
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