CPU underload

[Eugene Grosbein]

On 09.11.2015 02:23, Adrian Chadd wrote:

>>> Which MIPS kernel config doesn't have USB_HOST_ALIGN=64 ?
>>
>> sys/mips/conf/AR934X_BASE has USB_HOST_ALIGN=32

> ok, what's the l1 cache size reported at boot up?
> 
> I think I may just bump them all to 64.

That is TL-WDR3600, here is start of boot log:

U-Boot 1.1.4 (Jun  5 2015 - 14:14:34)

U-boot DB120


DRAM:  128 MB
id read 0x100000ff
flash size 8MB, sector count = 128
Flash:  8 MB
Using default environment

PCIe Reset OK!!!!!!
In:    serial
Out:   serial
Err:   serial
Net:   ag934x_enet_initialize...
No valid address in Flash. Using fixed address
 wasp  reset mask:c03300 
WASP  ----> S17 PHY *
: cfg1 0x7 cfg2 0x7114
eth0: ba:be:fa:ce:08:41
athrs17_reg_init: complete
eth0 up
eth0
Autobooting in 1 seconds
## Booting image at 9f020000 ...
   Uncompressing Kernel Image ... OK

Starting kernel ...

CPU platform: Atheros AR9344 rev 2
CPU Frequency=560 MHz
CPU DDR Frequency=450 MHz

CPU platform: Atheros AR9344 rev 2
CPU Frequency=560 MHz
CPU DDR Frequency=450 MHz
CPU AHB Frequency=225 MHz
platform frequency: 560 MHz
CPU reference clock: 40 MHz
CPU MDIO clock: 100 MHz
arguments: 
  a0 = 00000007
  a1 = a7f8ffb0
  a2 = 08000000
  a3 = 00000008
Cmd line:argv is invalid
Environment:
envp is invalid
Cache info:
  picache_stride    = 4096
  picache_loopcount = 16
  pdcache_stride    = 4096
  pdcache_loopcount = 8
cpu0: MIPS Technologies processor v76.151
  MMU: Standard TLB, 32 entries
  L1 i-cache: 4 ways of 512 sets, 32 bytes per line
  L1 d-cache: 4 ways of 256 sets, 32 bytes per line
  Config1=0xbee3519e<PerfCount,WatchRegs,MIPS16,EJTAG>
  Config3=0x2c20
Physical memory chunk(s):
0x47c000 - 0x7ffffff, 129515520 bytes (31620 pages)
Maxmem is 0x8000000