Bringing up mips74k support

[Adrian Chadd]

On 28 September 2013 02:33, Warner Losh <imp at bsdimp.com> wrote:

>
> On Sep 28, 2013, at 11:20 AM, Adrian Chadd wrote:
>
> > Hi,
> >
> > I'll post a patch soon, but the TL;DR version:
> >
> > * the CCA attributes are different on mips74k. I think the cached
> > attribtute is 0x0, rather than the default. Check the mips platform
> support
> > on netbsd - it has a special case for mips74k.
> > * The hazard should be EHB, not NOP or SSNOP
> > * .. should the hazard be SSNOP for mips24k, rather than "nop;nop;nop.."
> ?
> > * We're missing hazards around the TLB operations in various places in .c
> > and .S code, sigh.
>
> Not all TLB operations have hazards... :)  So I'd want to know if they are
> all needed.
>
> > But with the above, it's enough to bring the AR9344 up to mountroot> .
>
> Woot! Let's do a code review at EuroBSDCon....
>
>
So the brainstorm so far:

* Need to teach the cache coherency attributes about the mips74k
requirements;
* Need to identify exactly what COP0_SYNC and HAZARD should be for each CPU
family/type;
* Need to identify exactly where COP0_SYNC and HAZARD should be used for
each CPU family/type;
* Need to look at whether we should be using SSNOP in the delay slots after
various things (eg jumps.)

I'm reviewing the See Mips Run (2nd Ed) section on Hazards (Section 3.4.)
Hopefully Warner and I can figure this particular hilarity out.

Thanks,



-adrian