eventtimer issue on mips: temporary workaround

[Andrew Duane]

I've been running JC's patch on my Octeon blade for a while, and it does fix some serious problems. It's been very stable.

As to why "wait" wouldn't just return if an interrupt is asserted, I don't know. The MIPS manual is (deliberately?) vague on these details, but any software engineer can explain why that's needed to write correct software. Maybe the silicon engineers didn't listen?

 ...................................
Andrew Duane
Juniper Networks
o   +1 978 589 0551
m  +1 603-770-7088
aduane at juniper.net

 

> -----Original Message-----
> From: owner-freebsd-mips at freebsd.org [mailto:owner-freebsd-
> mips at freebsd.org] On Behalf Of Jayachandran C.
> Sent: Wednesday, September 28, 2011 11:42 PM
> To: Adrian Chadd
> Cc: freebsd-mips at freebsd.org
> Subject: Re: eventtimer issue on mips: temporary workaround
> 
> On Wed, Sep 28, 2011 at 10:06 PM, Adrian Chadd <adrian at freebsd.org>
> wrote:
> > .. so, the patch is totallyw rong.
> >
> > intr_disable() needs to be moved before critical_enter() or it
> doesn't
> > achieve anything.
> 
> I'm not able to figure out why...
> 
> > But the race is still there, between intr_enable() and "wait".
> > The only way to eliminate this race is to completely eliminate all
> the
> > code in cpu_idle().
> 
> the amd implementation seems to be using the STI instruction to enable
> interrupts - but I'm not able to see how to avoid this race condition
> on platforms which does not have a similar instruction.
> 
> > Would someone clued in the implementation of wait please step up and
> help? :)
> 
> What if go back to the earlier version of cpu_idle which does not have
> critical_enter() and cpu_idleclock() for now, or does this also have
> issues?
> 
> I had also seen issues on XLR  which went away when I took out
> 'ET_FLAGS_ONESHOT' from the mips clock event timer .  That is another
> possible workaround.
> 
> JC.
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