mips sig_atomic_t

[Tijl Coosemans]

On Sunday 12 December 2010 18:37:16 Warner Losh wrote:
> On 12/12/2010 06:17, Tijl Coosemans wrote:
>> In mips/include/signal.h sig_atomic_t is defined as int. Do you know if
>> this can be 64 bit on the N64 ABI like on other 64 bit archs? How about
>> N32? For reference, the POSIX definition of sig_atomic_t states: possibly
>> volatile-qualified integer type of an object that can be accessed as an
>> atomic entity, even in the presence of asynchronous interrupts.
> LD and SD can be used to load/store an aligned 64-bit word in a 
> mips64-like ISA.  For mips32 ISAs, a 64-bit quantity is loaded/stored 
> with two LW/SW instructions.
> 
> N64 and N32 can load/store these.  However, N32 has an int set to 
> 32-bits.  I think this is OK.

I'm still not sure if I understand the relations between the different
acronyms correctly. Are these statements correct?

There's a MIPS32 ISA and a MIPS64 ISA.

The O32 ABI is ILP32 running on MIPS32. Like any ordinary 32 bit arch.

The N64 ABI is LP64 running on MIPS64. Like any ordinary 64 bit arch.

The N32 ABI is ILP32 running on MIPS64. It's pure MIPS64 not a
compatibility mode or something like i386 code running on amd64. It has
64 bit registers and can do 64 bit load/store.
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