[RFC] Event timers on MIPS
Alexander Motin
mav at FreeBSD.org
Sun Aug 1 11:39:42 UTC 2010
Neel Natu wrote:
> Here is the patch for mips/mips/tick.c to fix tick_ticker().
>
> In addition to incorporating the changes made in rmi/tick.c it fixes
> the following:
>
> - There is a race between clock_intr() and tick_ticker() updating
> counter_upper and counter_lower_last. This race exists because
> interrupts are enabled even though tick_ticker() executes in a
> critical section.
While there is indeed a possible issue, I am not sure your solution is
reliable. I haven't looked how DPCPU_GET implemented on MIPS, but can't
compiler reorder them? I would thought about some lock or at least some
atomics with barriers.
"t_upper++;" there looks a bit strange, as it is not written back. The
wrapping stuff won't work if this timer interrupts were not used.
> - Fix a bug in clock_intr() in how it updates counter_upper and
> counter_lower_last. It updates it only once every time the COUNT
> register wraps around. More interestingly it will *never* update the
> cached values of 'counter_upper' and 'counter_lower_last' if the
> previous value of 'counter_lower_last' happens to be '0'.
Reasonable. It would be nice if both wrapping places were implemented
alike or the same way.
> - Get rid of the superfluous critical section in clock_intr(). There
> is no reason for it because clock_intr() executes in hard interrupt
> context.
Seems OK.
--
Alexander Motin
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