From neelnatu at yahoo.com Wed Jul 1 04:42:29 2009 From: neelnatu at yahoo.com (Neelkanth Natu) Date: Wed Jul 1 04:42:35 2009 Subject: Machine Check exception during bootup Message-ID: <14584.70267.qm@web34403.mail.mud.yahoo.com> Hi, I was seeing machine check exception with the 'TLB Shutdown' bit set in the Status register during bootup. This would happen about 30% of the time at exactly the same place in Mips_TLBUpdate(). I was able to track this down to a bug in Mips_TLBFlush() which was using whatever address happened to be in the EntryHi register to initialize the TLB. If this address happened to be one that the system would subsequently instantiate in the TLB we would hit a machine check exception in Mips_TLBUpdate(). At first glance it appears that the code in Mips_TLBUpdate() should deal with this since it does a TLB probe and if the probe is successful it will do a 'tlbwi' to avoid the machine check. But 'tlbp' can only look at the 'asid' and 'vpn2' fields to do its job - it does not know if you are planning to install a TLB entry with 'Global' scope. IMO this is why we trip up on a machine check exception at the 'tlbwr' instruction in Mips_TLBUpdate(). I am attaching the diff to tlb.S that fixes this problem. best Neel ==== //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/mips/tlb.S#1 - /amd/svlusr02.eng.netapp.com/vol/home24/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/tlb.S ==== @@ -81,14 +81,14 @@ #define _MFC0 dmfc0 #define _MTC0 dmtc0 #define WIRED_SHIFT 34 -#define PAGE_SHIFT 34 +#define PAGE_SHIFT 12 #else #define _SLL sll #define _SRL srl #define _MFC0 mfc0 #define _MTC0 mtc0 #define WIRED_SHIFT 2 -#define PAGE_SHIFT 2 +#define PAGE_SHIFT 12 #endif .set noreorder # Noreorder is default style! #if defined(ISA_MIPS32) @@ -232,22 +232,30 @@ mtc0 zero, COP_0_STATUS_REG # Disable interrupts ITLBNOPFIX mfc0 t1, COP_0_TLB_WIRED - li v0, MIPS_KSEG3_START + 0x0fff0000 # invalid address _MFC0 t0, COP_0_TLB_HI # Save the PID - _MTC0 v0, COP_0_TLB_HI # Mark entry high as invalid _MTC0 zero, COP_0_TLB_LO0 # Zero out low entry0. _MTC0 zero, COP_0_TLB_LO1 # Zero out low entry1. mtc0 zero, COP_0_TLB_PG_MASK # Zero out mask entry. + + # + # Load invalid entry, each TLB entry should have it's own bogus + # address calculated by following expression: + # MIPS_KSEG0_START + 0x0fff0000 + 2 * i * PAGE_SIZE; + # One bogus value for every TLB entry might cause MCHECK exception + # + sll t3, t1, PAGE_SHIFT + 1 + li v0, MIPS_KSEG0_START + 0x0fff0000 # invalid address + addu v0, t3 /* * Align the starting value (t1) and the upper bound (a0). */ 1: mtc0 t1, COP_0_TLB_INDEX # Set the index register. ITLBNOPFIX - _MTC0 t0, COP_0_TLB_HI # Restore the PID + _MTC0 v0, COP_0_TLB_HI # Mark entry high as invalid addu t1, t1, 1 # Increment index. - addu t0, t0, 8 * 1024 + addu v0, v0, 8 * 1024 MIPS_CPU_NOP_DELAY tlbwi # Write the TLB entry. MIPS_CPU_NOP_DELAY @@ -473,7 +481,17 @@ _MFC0 t4, COP_0_TLB_HI # Get current PID move t2, a0 mfc0 t1, COP_0_TLB_WIRED + + # + # Load invalid entry, each TLB entry should have it's own bogus + # address calculated by following expression: + # MIPS_KSEG0_START + 0x0fff0000 + 2 * i * PAGE_SIZE; + # One bogus value for every TLB entry might cause MCHECK exception + # + sll t3, t1, PAGE_SHIFT + 1 li v0, MIPS_KSEG0_START + 0x0fff0000 # invalid address + addu v0, t3 + mfc0 t3, COP_0_TLB_PG_MASK # save current pgMask # do {} while (t1 < t2) From imp at bsdimp.com Wed Jul 1 14:40:45 2009 From: imp at bsdimp.com (M. Warner Losh) Date: Wed Jul 1 14:40:52 2009 Subject: Machine Check exception during bootup In-Reply-To: <14584.70267.qm@web34403.mail.mud.yahoo.com> References: <14584.70267.qm@web34403.mail.mud.yahoo.com> Message-ID: <20090701.083900.1346819654.imp@bsdimp.com> In message: <14584.70267.qm@web34403.mail.mud.yahoo.com> Neelkanth Natu writes: : r02.eng.netapp.com/vol/home24/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/tlb.S ==== : @@ -81,14 +81,14 @@ : #define _MFC0 dmfc0 : #define _MTC0 dmtc0 : #define WIRED_SHIFT 34 : -#define PAGE_SHIFT 34 : +#define PAGE_SHIFT 12 : #else : #define _SLL sll : #define _SRL srl : #define _MFC0 mfc0 : #define _MTC0 mtc0 : #define WIRED_SHIFT 2 : -#define PAGE_SHIFT 2 : +#define PAGE_SHIFT 12 : #endif These are wrong. PAGE_SHIFT is supposed to be the bit position in the TLB, not the size of the page for multiplication. At least in thoery, but looking at the manual doesn't even bear that out... However, it appears it isn't used that way at all in the rest of the code. This means we should move it outside of the #ifdef, since it has nothing to do with ISA we're compiling for. : .set noreorder # Noreorder is default style! : #if defined(ISA_MIPS32) : @@ -232,22 +232,30 @@ : mtc0 zero, COP_0_STATUS_REG # Disable interrupts : ITLBNOPFIX : mfc0 t1, COP_0_TLB_WIRED : - li v0, MIPS_KSEG3_START + 0x0fff0000 # invalid address : _MFC0 t0, COP_0_TLB_HI # Save the PID : : - _MTC0 v0, COP_0_TLB_HI # Mark entry high as invalid : _MTC0 zero, COP_0_TLB_LO0 # Zero out low entry0. : _MTC0 zero, COP_0_TLB_LO1 # Zero out low entry1. : mtc0 zero, COP_0_TLB_PG_MASK # Zero out mask entry. : + : + # : + # Load invalid entry, each TLB entry should have it's own bogus : + # address calculated by following expression: : + # MIPS_KSEG0_START + 0x0fff0000 + 2 * i * PAGE_SIZE; : + # One bogus value for every TLB entry might cause MCHECK exception : + # : + sll t3, t1, PAGE_SHIFT + 1 : + li v0, MIPS_KSEG0_START + 0x0fff0000 # invalid address : + addu v0, t3 I'll note that NetBSD doesn't add the 0x0fff0000 on the end here. I don't understand why we do it, even though I likely added this to the port. Does it work without it? Warner From neelnatu at yahoo.com Thu Jul 2 03:28:11 2009 From: neelnatu at yahoo.com (Neelkanth Natu) Date: Thu Jul 2 03:28:22 2009 Subject: Machine Check exception during bootup Message-ID: <646809.32414.qm@web34401.mail.mud.yahoo.com> Hi Warner, Thanks for reviewing the diff. I have made the changes you suggested in the review. The new diffs are at the end of this email. - No need to have redefine PAGE_SIZE in tlb.S. I am now generating this macro via genassym.c - Remove the offset 0x0fff0000 used when invalidating tlb entries. I have tested this on MALTA as well as SWARM and it seems to work fine. best Neel ==== //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/mips/genassym.c#1 - /amd/svlusr02.eng.netapp.com/vol/home24/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/genassym.c ==== 93a94 > ASSYM(PAGE_SHIFT, PAGE_SHIFT); ==== //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/mips/tlb.S#1 - /amd/svlusr02.eng.netapp.com/vol/home24/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/tlb.S ==== 84d83 < #define PAGE_SHIFT 34 91d89 < #define PAGE_SHIFT 2 235d232 < li v0, MIPS_KSEG3_START + 0x0fff0000 # invalid address 238d234 < _MTC0 v0, COP_0_TLB_HI # Mark entry high as invalid 241a238,247 > > # > # Load invalid entry, each TLB entry should have it's own bogus > # address calculated by following expression: > # MIPS_KSEG0_START + 2 * i * PAGE_SIZE; > # One bogus value for every TLB entry might cause MCHECK exception > # > sll t3, t1, PAGE_SHIFT + 1 > li v0, MIPS_KSEG0_START # invalid address > addu v0, t3 248c254 < _MTC0 t0, COP_0_TLB_HI # Restore the PID --- > _MTC0 v0, COP_0_TLB_HI # Mark entry high as invalid 250c256 < addu t0, t0, 8 * 1024 --- > addu v0, v0, 8 * 1024 292c298 < li t1, MIPS_KSEG0_START + 0x0fff0000 --- > li t1, MIPS_KSEG0_START 297c303 < # MIPS_KSEG0_START + 0x0fff0000 + 2 * i * PAGE_SIZE; --- > # MIPS_KSEG0_START + 2 * i * PAGE_SIZE; 476c482,492 < li v0, MIPS_KSEG0_START + 0x0fff0000 # invalid address --- > > # > # Load invalid entry, each TLB entry should have it's own bogus > # address calculated by following expression: > # MIPS_KSEG0_START + 2 * i * PAGE_SIZE; > # One bogus value for every TLB entry might cause MCHECK exception > # > sll t3, t1, PAGE_SHIFT + 1 > li v0, MIPS_KSEG0_START # invalid address > addu v0, t3 > ==== //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/mips/swtch.S#1 - /amd/svlusr02.eng.netapp.com/vol/home24/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/swtch.S ==== 84d83 < #define PAGE_SHIFT 34 91d89 < #define PAGE_SHIFT 2 364c362 < li t1, MIPS_KSEG0_START + 0x0fff0000 # invalidate tlb entry --- > li t1, MIPS_KSEG0_START # invalidate tlb entry --- On Wed, 7/1/09, M. Warner Losh wrote: > From: M. Warner Losh > Subject: Re: Machine Check exception during bootup > To: neelnatu@yahoo.com > Cc: freebsd-mips@freebsd.org > Date: Wednesday, July 1, 2009, 7:39 AM > In message: <14584.70267.qm@web34403.mail.mud.yahoo.com> > Neelkanth Natu > > writes: > : > r02.eng.netapp.com/vol/home24/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/tlb.S > ==== > : @@ -81,14 +81,14 @@ > : #define _MFC0 > dmfc0 > : #define _MTC0 > dmtc0 > : #define WIRED_SHIFT 34 > : -#define PAGE_SHIFT 34 > : +#define PAGE_SHIFT 12 > : #else > : #define _SLL sll > : #define _SRL > srl > : #define _MFC0 > mfc0 > : #define _MTC0 > mtc0 > : #define WIRED_SHIFT 2 > : -#define PAGE_SHIFT 2 > : +#define PAGE_SHIFT 12 > : #endif > > These are wrong. PAGE_SHIFT is supposed to be the bit > position in the > TLB, not the size of the page for multiplication. At > least in thoery, > but looking at the manual doesn't even bear that out... > > However, it appears it isn't used that way at all in the > rest of the > code. This means we should move it outside of the > #ifdef, since it > has nothing to do with ISA we're compiling for. > > : .set > noreorder > # Noreorder is default style! > : #if defined(ISA_MIPS32) > : @@ -232,22 +232,30 @@ > : mtc0 zero, > COP_0_STATUS_REG # > Disable interrupts > : ITLBNOPFIX > : mfc0 t1, > COP_0_TLB_WIRED > : - li v0, > MIPS_KSEG3_START + 0x0fff0000 # invalid address > : _MFC0 t0, > COP_0_TLB_HI # Save the > PID > : > : - _MTC0 v0, > COP_0_TLB_HI # Mark > entry high as invalid > : _MTC0 zero, > COP_0_TLB_LO0 # Zero > out low entry0. > : _MTC0 zero, > COP_0_TLB_LO1 # Zero > out low entry1. > : mtc0 zero, > COP_0_TLB_PG_MASK # Zero out mask entry. > : + > : + # > : + # Load invalid entry, each TLB entry > should have it's own bogus > : + # address calculated by following > expression: > : + # MIPS_KSEG0_START + 0x0fff0000 + 2 * > i * PAGE_SIZE; > : + # One bogus value for every TLB entry > might cause MCHECK exception > : + # > : + sll t3, t1, > PAGE_SHIFT + 1 > : + li v0, > MIPS_KSEG0_START + 0x0fff0000 # invalid > address > : + addu v0, t3 > > I'll note that NetBSD doesn't add the 0x0fff0000 on the end > here. I > don't understand why we do it, even though I likely added > this to the > port. Does it work without it? > > Warner > From imp at bsdimp.com Thu Jul 2 03:40:23 2009 From: imp at bsdimp.com (M. Warner Losh) Date: Thu Jul 2 03:40:30 2009 Subject: Machine Check exception during bootup In-Reply-To: <646809.32414.qm@web34401.mail.mud.yahoo.com> References: <646809.32414.qm@web34401.mail.mud.yahoo.com> Message-ID: <20090701.213914.656669320.imp@bsdimp.com> In message: <646809.32414.qm@web34401.mail.mud.yahoo.com> Neelkanth Natu writes: : : Hi Warner, : : Thanks for reviewing the diff. : : I have made the changes you suggested in the review. The new diffs are : at the end of this email. : : - No need to have redefine PAGE_SIZE in tlb.S. I am now generating : this macro via genassym.c : : - Remove the offset 0x0fff0000 used when invalidating tlb entries. I have : tested this on MALTA as well as SWARM and it seems to work fine. Yes. You fixed the real bug, I think, when you moved from KSEG3 to KSEG0. I think there's still some things wrong with some of these routines. I'll send what I have, if I have something better, in a few. I think this is an excellent start. : best : Neel : : ==== //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/mips/genassym.c#1 - /amd/svlusr02.eng.netapp.com/vol/home24/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/genassym.c ==== : 93a94 : > ASSYM(PAGE_SHIFT, PAGE_SHIFT); : ==== //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/mips/tlb.S#1 - /amd/svlusr02.eng.netapp.com/vol/home24/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/tlb.S ==== : 84d83 : < #define PAGE_SHIFT 34 Can you resend as a unified diff? Warner : 91d89 : < #define PAGE_SHIFT 2 : 235d232 : < li v0, MIPS_KSEG3_START + 0x0fff0000 # invalid address : 238d234 : < _MTC0 v0, COP_0_TLB_HI # Mark entry high as invalid : 241a238,247 : > : > # : > # Load invalid entry, each TLB entry should have it's own bogus : > # address calculated by following expression: : > # MIPS_KSEG0_START + 2 * i * PAGE_SIZE; : > # One bogus value for every TLB entry might cause MCHECK exception : > # : > sll t3, t1, PAGE_SHIFT + 1 : > li v0, MIPS_KSEG0_START # invalid address : > addu v0, t3 : 248c254 : < _MTC0 t0, COP_0_TLB_HI # Restore the PID : --- : > _MTC0 v0, COP_0_TLB_HI # Mark entry high as invalid : 250c256 : < addu t0, t0, 8 * 1024 : --- : > addu v0, v0, 8 * 1024 : 292c298 : < li t1, MIPS_KSEG0_START + 0x0fff0000 : --- : > li t1, MIPS_KSEG0_START : 297c303 : < # MIPS_KSEG0_START + 0x0fff0000 + 2 * i * PAGE_SIZE; : --- : > # MIPS_KSEG0_START + 2 * i * PAGE_SIZE; : 476c482,492 : < li v0, MIPS_KSEG0_START + 0x0fff0000 # invalid address : --- : > : > # : > # Load invalid entry, each TLB entry should have it's own bogus : > # address calculated by following expression: : > # MIPS_KSEG0_START + 2 * i * PAGE_SIZE; : > # One bogus value for every TLB entry might cause MCHECK exception : > # : > sll t3, t1, PAGE_SHIFT + 1 : > li v0, MIPS_KSEG0_START # invalid address : > addu v0, t3 : > : ==== //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/mips/swtch.S#1 - /amd/svlusr02.eng.netapp.com/vol/home24/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/swtch.S ==== : 84d83 : < #define PAGE_SHIFT 34 : 91d89 : < #define PAGE_SHIFT 2 : 364c362 : < li t1, MIPS_KSEG0_START + 0x0fff0000 # invalidate tlb entry : --- : > li t1, MIPS_KSEG0_START # invalidate tlb entry : : : --- On Wed, 7/1/09, M. Warner Losh wrote: : : > From: M. Warner Losh : > Subject: Re: Machine Check exception during bootup : > To: neelnatu@yahoo.com : > Cc: freebsd-mips@freebsd.org : > Date: Wednesday, July 1, 2009, 7:39 AM : > In message: <14584.70267.qm@web34403.mail.mud.yahoo.com> : > Neelkanth Natu : > : > writes: : > : : > r02.eng.netapp.com/vol/home24/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/tlb.S : > ==== : > : @@ -81,14 +81,14 @@ : > : #define _MFC0 : > dmfc0 : > : #define _MTC0 : > dmtc0 : > : #define WIRED_SHIFT 34 : > : -#define PAGE_SHIFT 34 : > : +#define PAGE_SHIFT 12 : > : #else : > : #define _SLL sll : > : #define _SRL : > srl : > : #define _MFC0 : > mfc0 : > : #define _MTC0 : > mtc0 : > : #define WIRED_SHIFT 2 : > : -#define PAGE_SHIFT 2 : > : +#define PAGE_SHIFT 12 : > : #endif : > : > These are wrong. PAGE_SHIFT is supposed to be the bit : > position in the : > TLB, not the size of the page for multiplication. At : > least in thoery, : > but looking at the manual doesn't even bear that out... : > : > However, it appears it isn't used that way at all in the : > rest of the : > code. This means we should move it outside of the : > #ifdef, since it : > has nothing to do with ISA we're compiling for. : > : > : .set : > noreorder : > # Noreorder is default style! : > : #if defined(ISA_MIPS32) : > : @@ -232,22 +232,30 @@ : > : mtc0 zero, : > COP_0_STATUS_REG # : > Disable interrupts : > : ITLBNOPFIX : > : mfc0 t1, : > COP_0_TLB_WIRED : > : - li v0, : > MIPS_KSEG3_START + 0x0fff0000 # invalid address : > : _MFC0 t0, : > COP_0_TLB_HI # Save the : > PID : > : : > : - _MTC0 v0, : > COP_0_TLB_HI # Mark : > entry high as invalid : > : _MTC0 zero, : > COP_0_TLB_LO0 # Zero : > out low entry0. : > : _MTC0 zero, : > COP_0_TLB_LO1 # Zero : > out low entry1. : > : mtc0 zero, : > COP_0_TLB_PG_MASK # Zero out mask entry. : > : + : > : + # : > : + # Load invalid entry, each TLB entry : > should have it's own bogus : > : + # address calculated by following : > expression: : > : + # MIPS_KSEG0_START + 0x0fff0000 + 2 * : > i * PAGE_SIZE; : > : + # One bogus value for every TLB entry : > might cause MCHECK exception : > : + # : > : + sll t3, t1, : > PAGE_SHIFT + 1 : > : + li v0, : > MIPS_KSEG0_START + 0x0fff0000 # invalid : > address : > : + addu v0, t3 : > : > I'll note that NetBSD doesn't add the 0x0fff0000 on the end : > here. I : > don't understand why we do it, even though I likely added : > this to the : > port. Does it work without it? : > : > Warner : > : : : : : From neelnatu at yahoo.com Thu Jul 2 03:49:02 2009 From: neelnatu at yahoo.com (Neelkanth Natu) Date: Thu Jul 2 03:49:09 2009 Subject: Machine Check exception during bootup Message-ID: <122643.47019.qm@web34403.mail.mud.yahoo.com> Hi Warner, Here is the unified diff: ==== //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/mips/genassym.c#1 - /u/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/genassym.c ==== @@ -91,6 +91,7 @@ ASSYM(SIGF_UC, offsetof(struct sigframe, sf_uc)); ASSYM(SIGFPE, SIGFPE); ASSYM(PGSHIFT, PGSHIFT); +ASSYM(PAGE_SHIFT, PAGE_SHIFT); ASSYM(NBPG, NBPG); ASSYM(SEGSHIFT, SEGSHIFT); ASSYM(NPTEPG, NPTEPG); ==== //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/mips/tlb.S#1 - /u/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/tlb.S ==== @@ -81,14 +81,12 @@ #define _MFC0 dmfc0 #define _MTC0 dmtc0 #define WIRED_SHIFT 34 -#define PAGE_SHIFT 34 #else #define _SLL sll #define _SRL srl #define _MFC0 mfc0 #define _MTC0 mtc0 #define WIRED_SHIFT 2 -#define PAGE_SHIFT 2 #endif .set noreorder # Noreorder is default style! #if defined(ISA_MIPS32) @@ -232,22 +230,30 @@ mtc0 zero, COP_0_STATUS_REG # Disable interrupts ITLBNOPFIX mfc0 t1, COP_0_TLB_WIRED - li v0, MIPS_KSEG3_START + 0x0fff0000 # invalid address _MFC0 t0, COP_0_TLB_HI # Save the PID - _MTC0 v0, COP_0_TLB_HI # Mark entry high as invalid _MTC0 zero, COP_0_TLB_LO0 # Zero out low entry0. _MTC0 zero, COP_0_TLB_LO1 # Zero out low entry1. mtc0 zero, COP_0_TLB_PG_MASK # Zero out mask entry. + + # + # Load invalid entry, each TLB entry should have it's own bogus + # address calculated by following expression: + # MIPS_KSEG0_START + 2 * i * PAGE_SIZE; + # One bogus value for every TLB entry might cause MCHECK exception + # + sll t3, t1, PAGE_SHIFT + 1 + li v0, MIPS_KSEG0_START # invalid address + addu v0, t3 /* * Align the starting value (t1) and the upper bound (a0). */ 1: mtc0 t1, COP_0_TLB_INDEX # Set the index register. ITLBNOPFIX - _MTC0 t0, COP_0_TLB_HI # Restore the PID + _MTC0 v0, COP_0_TLB_HI # Mark entry high as invalid addu t1, t1, 1 # Increment index. - addu t0, t0, 8 * 1024 + addu v0, v0, 8 * 1024 MIPS_CPU_NOP_DELAY tlbwi # Write the TLB entry. MIPS_CPU_NOP_DELAY @@ -289,12 +295,12 @@ tlbp # Probe for the entry. MIPS_CPU_NOP_DELAY mfc0 v0, COP_0_TLB_INDEX # See what we got - li t1, MIPS_KSEG0_START + 0x0fff0000 + li t1, MIPS_KSEG0_START bltz v0, 1f # index < 0 => !found nop # Load invalid entry, each TLB entry should have it's own bogus # address calculated by following expression: - # MIPS_KSEG0_START + 0x0fff0000 + 2 * i * PAGE_SIZE; + # MIPS_KSEG0_START + 2 * i * PAGE_SIZE; # One bogus value for every TLB entry might cause MCHECK exception sll v0, PAGE_SHIFT + 1 addu t1, v0 @@ -473,7 +479,17 @@ _MFC0 t4, COP_0_TLB_HI # Get current PID move t2, a0 mfc0 t1, COP_0_TLB_WIRED - li v0, MIPS_KSEG0_START + 0x0fff0000 # invalid address + + # + # Load invalid entry, each TLB entry should have it's own bogus + # address calculated by following expression: + # MIPS_KSEG0_START + 2 * i * PAGE_SIZE; + # One bogus value for every TLB entry might cause MCHECK exception + # + sll t3, t1, PAGE_SHIFT + 1 + li v0, MIPS_KSEG0_START # invalid address + addu v0, t3 + mfc0 t3, COP_0_TLB_PG_MASK # save current pgMask # do {} while (t1 < t2) ==== //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/mips/swtch.S#1 - /u/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/swtch.S ==== @@ -81,14 +81,12 @@ #define _MFC0 dmfc0 #define _MTC0 dmtc0 #define WIRED_SHIFT 34 -#define PAGE_SHIFT 34 #else #define _SLL sll #define _SRL srl #define _MFC0 mfc0 #define _MTC0 mtc0 #define WIRED_SHIFT 2 -#define PAGE_SHIFT 2 #endif .set noreorder # Noreorder is default style! #if defined(ISA_MIPS32) @@ -361,7 +359,7 @@ nop pgm: bltz s0, entry0set - li t1, MIPS_KSEG0_START + 0x0fff0000 # invalidate tlb entry + li t1, MIPS_KSEG0_START # invalidate tlb entry sll s0, PAGE_SHIFT + 1 addu t1, s0 mtc0 t1, COP_0_TLB_HI --- On Wed, 7/1/09, M. Warner Losh wrote: > From: M. Warner Losh > Subject: Re: Machine Check exception during bootup > To: neelnatu@yahoo.com > Cc: freebsd-mips@freebsd.org > Date: Wednesday, July 1, 2009, 8:39 PM > In message: <646809.32414.qm@web34401.mail.mud.yahoo.com> > Neelkanth Natu > > writes: > : > : Hi Warner, > : > : Thanks for reviewing the diff. > : > : I have made the changes you suggested in the review. The > new diffs are > : at the end of this email. > : > : - No need to have redefine PAGE_SIZE in tlb.S. I am now > generating > : this macro via genassym.c > : > : - Remove the offset 0x0fff0000 used when invalidating tlb > entries. I have > : tested this on MALTA as well as SWARM > and it seems to work fine. > > Yes. You fixed the real bug, I think, when you moved > from KSEG3 to > KSEG0. I think there's still some things wrong with > some of these > routines. I'll send what I have, if I have something > better, in a > few. I think this is an excellent start. > > : best > : Neel > : > : ==== > //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/mips/genassym.c#1 > - > /amd/svlusr02.eng.netapp.com/vol/home24/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/genassym.c > ==== > : 93a94 > : > ASSYM(PAGE_SHIFT, PAGE_SHIFT); > : ==== > //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/mips/tlb.S#1 > - > /amd/svlusr02.eng.netapp.com/vol/home24/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/tlb.S > ==== > : 84d83 > : < #define PAGE_SHIFT 34 > > Can you resend as a unified diff? > > Warner > > > : 91d89 > : < #define PAGE_SHIFT 2 > : 235d232 > : < li v0, > MIPS_KSEG3_START + 0x0fff0000 # invalid address > : 238d234 > : < _MTC0 v0, > COP_0_TLB_HI # Mark > entry high as invalid > : 241a238,247 > : > > : > # > : > # Load invalid entry, each TLB > entry should have it's own bogus > : > # address calculated by following > expression: > : > # MIPS_KSEG0_START + 2 * i * > PAGE_SIZE; > : > # One bogus value for every TLB > entry might cause MCHECK exception > : > # > : > sll t3, t1, > PAGE_SHIFT + 1 > : > li v0, > MIPS_KSEG0_START # > invalid address > : > addu v0, t3 > : 248c254 > : < _MTC0 t0, > COP_0_TLB_HI # Restore > the PID > : --- > : > _MTC0 v0, > COP_0_TLB_HI # Mark > entry high as invalid > : 250c256 > : < addu t0, t0, 8 > * 1024 > : --- > : > addu v0, v0, 8 > * 1024 > : 292c298 > : < li t1, > MIPS_KSEG0_START + 0x0fff0000 > : --- > : > li t1, > MIPS_KSEG0_START > : 297c303 > : < # MIPS_KSEG0_START + 0x0fff0000 + > 2 * i * PAGE_SIZE; > : --- > : > # MIPS_KSEG0_START + 2 * i * > PAGE_SIZE; > : 476c482,492 > : < li v0, > MIPS_KSEG0_START + 0x0fff0000 # invalid > address > : --- > : > > : > # > : > # Load invalid entry, each TLB > entry should have it's own bogus > : > # address calculated by following > expression: > : > # MIPS_KSEG0_START + 2 * i * > PAGE_SIZE; > : > # One bogus value for every TLB > entry might cause MCHECK exception > : > # > : > sll t3, t1, > PAGE_SHIFT + 1 > : > li v0, > MIPS_KSEG0_START # > invalid address > : > addu v0, t3 > : > > : ==== > //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/mips/swtch.S#1 > - > /amd/svlusr02.eng.netapp.com/vol/home24/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/swtch.S > ==== > : 84d83 > : < #define PAGE_SHIFT 34 > : 91d89 > : < #define PAGE_SHIFT 2 > : 364c362 > : < li t1, > MIPS_KSEG0_START + 0x0fff0000 # invalidate > tlb entry > : --- > : > li t1, > MIPS_KSEG0_START # > invalidate tlb entry > : > : > : --- On Wed, 7/1/09, M. Warner Losh > wrote: > : > : > From: M. Warner Losh > : > Subject: Re: Machine Check exception during bootup > : > To: neelnatu@yahoo.com > : > Cc: freebsd-mips@freebsd.org > : > Date: Wednesday, July 1, 2009, 7:39 AM > : > In message: <14584.70267.qm@web34403.mail.mud.yahoo.com> > : > > Neelkanth Natu > : > > : > writes: > : > : > : > > r02.eng.netapp.com/vol/home24/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/tlb.S > : > ==== > : > : @@ -81,14 +81,14 @@ > : > : #define > _MFC0 > : > dmfc0 > : > : #define > _MTC0 > : > dmtc0 > : > : #define WIRED_SHIFT 34 > : > : -#define PAGE_SHIFT 34 > : > : +#define PAGE_SHIFT 12 > : > : #else > : > : #define _SLL sll > : > : #define _SRL > : > srl > : > : #define > _MFC0 > : > mfc0 > : > : #define > _MTC0 > : > mtc0 > : > : #define WIRED_SHIFT 2 > : > : -#define PAGE_SHIFT 2 > : > : +#define PAGE_SHIFT 12 > : > : #endif > : > > : > These are wrong. PAGE_SHIFT is supposed to be > the bit > : > position in the > : > TLB, not the size of the page for > multiplication. At > : > least in thoery, > : > but looking at the manual doesn't even bear that > out... > : > > : > However, it appears it isn't used that way at all in > the > : > rest of the > : > code. This means we should move it outside of > the > : > #ifdef, since it > : > has nothing to do with ISA we're compiling for. > : > > : > : .set > : > noreorder > : > # Noreorder is default > style! > : > : #if defined(ISA_MIPS32) > : > : @@ -232,22 +232,30 @@ > : > : mtc0 zero, > : > COP_0_STATUS_REG # > : > Disable interrupts > : > : ITLBNOPFIX > : > : mfc0 t1, > : > COP_0_TLB_WIRED > : > : - li v0, > : > MIPS_KSEG3_START + 0x0fff0000 # invalid address > : > : _MFC0 t0, > : > COP_0_TLB_HI # Save the > : > PID > : > : > : > : - _MTC0 v0, > : > COP_0_TLB_HI # Mark > : > entry high as invalid > : > : _MTC0 zero, > : > COP_0_TLB_LO0 # Zero > : > out low entry0. > : > : _MTC0 zero, > : > COP_0_TLB_LO1 # Zero > : > out low entry1. > : > : mtc0 zero, > : > COP_0_TLB_PG_MASK # Zero out > mask entry. > : > : + > : > : + # > : > : + # Load invalid entry, each TLB > entry > : > should have it's own bogus > : > : + # address calculated by following > : > expression: > : > : + # MIPS_KSEG0_START + 0x0fff0000 + 2 > * > : > i * PAGE_SIZE; > : > : + # One bogus value for every TLB > entry > : > might cause MCHECK exception > : > : + # > : > : + sll t3, t1, > : > PAGE_SHIFT + 1 > : > : + li v0, > : > MIPS_KSEG0_START + 0x0fff0000 # > invalid > : > address > : > : + addu v0, t3 > : > > : > I'll note that NetBSD doesn't add the 0x0fff0000 on > the end > : > here. I > : > don't understand why we do it, even though I likely > added > : > this to the > : > port. Does it work without it? > : > > : > Warner > : > > : > : > : > : > : > From imp at bsdimp.com Sat Jul 4 03:13:33 2009 From: imp at bsdimp.com (M. Warner Losh) Date: Sat Jul 4 03:13:38 2009 Subject: Machine Check exception during bootup In-Reply-To: <122643.47019.qm@web34403.mail.mud.yahoo.com> References: <122643.47019.qm@web34403.mail.mud.yahoo.com> Message-ID: <20090703.211143.1622554029.imp@bsdimp.com> In message: <122643.47019.qm@web34403.mail.mud.yahoo.com> Neelkanth Natu writes: : ==== //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/mips/genassym.c#1 - /u/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/genassym.c ==== : @@ -91,6 +91,7 @@ : ASSYM(SIGF_UC, offsetof(struct sigframe, sf_uc)); : ASSYM(SIGFPE, SIGFPE); : ASSYM(PGSHIFT, PGSHIFT); : +ASSYM(PAGE_SHIFT, PAGE_SHIFT); : ASSYM(NBPG, NBPG); : ASSYM(SEGSHIFT, SEGSHIFT); : ASSYM(NPTEPG, NPTEPG); How do PAGE_SHIFT and PGSHIFT differ? Warner From neelnatu at yahoo.com Sat Jul 4 05:04:34 2009 From: neelnatu at yahoo.com (Neelkanth Natu) Date: Sat Jul 4 05:04:41 2009 Subject: Machine Check exception during bootup Message-ID: <385015.11949.qm@web34404.mail.mud.yahoo.com> Hi Warner, --- On Fri, 7/3/09, M. Warner Losh wrote: > From: M. Warner Losh > Subject: Re: Machine Check exception during bootup > To: neelnatu@yahoo.com > Cc: freebsd-mips@freebsd.org > Date: Friday, July 3, 2009, 8:11 PM > In message: <122643.47019.qm@web34403.mail.mud.yahoo.com> > Neelkanth Natu > > writes: > : ==== > //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/mips/genassym.c#1 > - /u/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/genassym.c > ==== > : @@ -91,6 +91,7 @@ > : ASSYM(SIGF_UC, offsetof(struct sigframe, sf_uc)); > : ASSYM(SIGFPE, SIGFPE); > : ASSYM(PGSHIFT, PGSHIFT); > : +ASSYM(PAGE_SHIFT, PAGE_SHIFT); > : ASSYM(NBPG, NBPG); > : ASSYM(SEGSHIFT, SEGSHIFT); > : ASSYM(NPTEPG, NPTEPG); > > How do PAGE_SHIFT and PGSHIFT differ? They are identical. I looked at other architectures and it seems that PGSHIFT is a macro defined for mips alone. The same is true for PGOFSET and PAGE_MASK. So I went with the obvious macro - PAGE_SHIFT. I think we should toast PGSHIFT and PGOFFSET and replace them with PAGE_SHIFT and PAGE_MASK respectively. What do you think? best Neel > > Warner > From imp at bsdimp.com Sat Jul 4 15:28:54 2009 From: imp at bsdimp.com (M. Warner Losh) Date: Sat Jul 4 15:29:00 2009 Subject: Machine Check exception during bootup In-Reply-To: <385015.11949.qm@web34404.mail.mud.yahoo.com> References: <385015.11949.qm@web34404.mail.mud.yahoo.com> Message-ID: <20090704.092559.353389034.imp@bsdimp.com> In message: <385015.11949.qm@web34404.mail.mud.yahoo.com> Neelkanth Natu writes: : : Hi Warner, : : --- On Fri, 7/3/09, M. Warner Losh wrote: : : > From: M. Warner Losh : > Subject: Re: Machine Check exception during bootup : > To: neelnatu@yahoo.com : > Cc: freebsd-mips@freebsd.org : > Date: Friday, July 3, 2009, 8:11 PM : > In message: <122643.47019.qm@web34403.mail.mud.yahoo.com> : > Neelkanth Natu : > : > writes: : > : ==== : > //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/mips/genassym.c#1 : > - /u/neelnatu/p4/freebsd_sibyte/src/sys/mips/mips/genassym.c : > ==== : > : @@ -91,6 +91,7 @@ : > : ASSYM(SIGF_UC, offsetof(struct sigframe, sf_uc)); : > : ASSYM(SIGFPE, SIGFPE); : > : ASSYM(PGSHIFT, PGSHIFT); : > : +ASSYM(PAGE_SHIFT, PAGE_SHIFT); : > : ASSYM(NBPG, NBPG); : > : ASSYM(SEGSHIFT, SEGSHIFT); : > : ASSYM(NPTEPG, NPTEPG); : > : > How do PAGE_SHIFT and PGSHIFT differ? : : They are identical. I looked at other architectures and it seems that : PGSHIFT is a macro defined for mips alone. The same is true for : PGOFSET and PAGE_MASK. : : So I went with the obvious macro - PAGE_SHIFT. : : I think we should toast PGSHIFT and PGOFFSET and replace them with : PAGE_SHIFT and PAGE_MASK respectively. What do you think? This sounds like a good cleanup item... Warner From communications_msn_cs_ptbr at Microsoft.msn.com Tue Jul 7 05:32:10 2009 From: communications_msn_cs_ptbr at Microsoft.msn.com (Equipe Windows Live) Date: Tue Jul 7 05:32:42 2009 Subject: Ultimo aviso seu email Hotmail sera excluido em ate 24 horas. Message-ID: <200907070504.n6752hR2022858@venkobrasil.com.br> Caso n?o esteja visualizando este e-mail, clique aqui Caro usu?rio, sua caixa de mensagens eletr?nicas ( e-mail ) est? em processo de exclus?o dentro de 48 horas se n?o for efetuada a revalida??o, ele ser? infelizmente deletado do Hotmail. Para sua Tranq?ilidade, voc? pode optar por validar ou cancelar. Siga as instru??es: Revalidar o correio eletr?nico: O processo para revalidar ser? efetuado ap?s a entrada em nosso link, para revalidar, clique abaixo e depois v? em abrir. Revalidar Correio eletr?nico: Ativar Conta Cancelar o correio eletr?nico: Se voc? optar por cancelar, voc? pode esperar 48 horas que ser? automaticamente deletado do sistema, ou clique abaixo e depois v? em abrir. Cancelar o Correio eletr?nico: Cancelar Conta Este e-mail ? apenas informativo, serve unicamente como notifica??o, n?o responda. Equipe Hotmail 2009 Microsoft e seus fornecedores. Todos os direitos reservados From tinderbox at freebsd.org Fri Jul 10 14:42:08 2009 From: tinderbox at freebsd.org (FreeBSD Tinderbox) Date: Fri Jul 10 14:42:20 2009 Subject: [head tinderbox] failure on mips/mips Message-ID: <20090710144204.1E4C17302F@freebsd-current.sentex.ca> TB --- 2009-07-10 13:46:27 - tinderbox 2.6 running on freebsd-current.sentex.ca TB --- 2009-07-10 13:46:27 - starting HEAD tinderbox run for mips/mips TB --- 2009-07-10 13:46:27 - cleaning the object tree TB --- 2009-07-10 13:46:48 - cvsupping the source tree TB --- 2009-07-10 13:46:48 - /usr/bin/csup -z -r 3 -g -L 1 -h localhost -s /tinderbox/HEAD/mips/mips/supfile TB --- 2009-07-10 13:46:57 - building world TB --- 2009-07-10 13:46:57 - MAKEOBJDIRPREFIX=/obj TB --- 2009-07-10 13:46:57 - PATH=/usr/bin:/usr/sbin:/bin:/sbin TB --- 2009-07-10 13:46:57 - TARGET=mips TB --- 2009-07-10 13:46:57 - TARGET_ARCH=mips TB --- 2009-07-10 13:46:57 - TZ=UTC TB --- 2009-07-10 13:46:57 - __MAKE_CONF=/dev/null TB --- 2009-07-10 13:46:57 - cd /src TB --- 2009-07-10 13:46:57 - /usr/bin/make -B buildworld >>> World build started on Fri Jul 10 13:46:58 UTC 2009 >>> Rebuilding the temporary build tree >>> stage 1.1: legacy release compatibility shims >>> stage 1.2: bootstrap tools >>> stage 2.1: cleaning up the object tree >>> stage 2.2: rebuilding the object tree >>> stage 2.3: build tools >>> stage 3: cross tools >>> stage 4.1: building includes >>> stage 4.2: building libraries >>> stage 4.3: make dependencies >>> stage 4.4: building everything [...] cc -O -pipe -EL -msoft-float -G0 -mno-dsp -mabicalls -std=gnu99 -Wsystem-headers -Werror -Wall -Wno-format-y2k -Wno-uninitialized -Wno-pointer-sign -Wl,-EL -o bsdlabel bsdlabel.o geom_bsd_enc.o -lgeom -lbsdxml -lsbuf gzip -cn /src/sbin/bsdlabel/bsdlabel.8 > bsdlabel.8.gz ===> sbin/camcontrol (all) cc -O -pipe -EL -msoft-float -G0 -mno-dsp -mabicalls -std=gnu99 -Wsystem-headers -Werror -Wall -Wno-format-y2k -W -Wno-unused-parameter -Wstrict-prototypes -Wmissing-prototypes -Wpointer-arith -Wreturn-type -Wcast-qual -Wwrite-strings -Wswitch -Wshadow -Wcast-align -Wunused-parameter -Wchar-subscripts -Winline -Wnested-externs -Wredundant-decls -Wno-pointer-sign -c /src/sbin/camcontrol/camcontrol.c cc1: warnings being treated as errors /src/sbin/camcontrol/camcontrol.c: In function 'ataidentify': /src/sbin/camcontrol/camcontrol.c:1195: warning: cast increases required alignment of target type /src/sbin/camcontrol/camcontrol.c:1196: warning: cast increases required alignment of target type *** Error code 1 Stop in /src/sbin/camcontrol. *** Error code 1 Stop in /src/sbin. *** Error code 1 Stop in /src. *** Error code 1 Stop in /src. *** Error code 1 Stop in /src. TB --- 2009-07-10 14:42:03 - WARNING: /usr/bin/make returned exit code 1 TB --- 2009-07-10 14:42:03 - ERROR: failed to build world TB --- 2009-07-10 14:42:03 - 2566.90 user 306.38 system 3336.03 real http://tinderbox.des.no/tinderbox-head-HEAD-mips-mips.full From Toby at IACmusic.com Sat Jul 11 08:53:07 2009 From: Toby at IACmusic.com (Toby@IACmusic.com) Date: Sat Jul 11 08:54:16 2009 Subject: Finally, a song contest that is free to enter. $27, 000+ in prizes too! Message-ID: Hi, IACmusic.com has started a major song contest and this one you can enter for free! &n throwing a party that Got a song be a lot of It's our [1]YEAR OF THE I "Indiependents" Day July 4th!&nb categories to choose from to enter your song in, including Songwri ting. The Grand Prize is a huge package that includes $1000 wor th of musical equipment (whatever you need), 2 weeks stay in a c ondo suite at your choice of a number of US vacation spots, an i Pod Shuffle, and a IAC Prime Perpetual Lifetime membership. But there are also 3 nice prizes in each of 16 categories and you can en exposur competition. He will hit Go [3]here Good luc The Staff at IACmusic.com (the Ind References 1. file://localhost/tmp/3D"htt 2. 3D"http://iacmusic.com/quickSignup.aspx" 3. file://localhost/tmp/3D From invitations at boxbe.com Sat Jul 11 13:10:29 2009 From: invitations at boxbe.com (Mario Augusto Mania) Date: Sat Jul 11 13:10:38 2009 Subject: Mario Augusto Mania added you as a friend on Boxbe Message-ID: <597745892.11823607.1247316742462.JavaMail.prod@app002.boxbe.com> Skipped content of type multipart/related From neelnatu at yahoo.com Tue Jul 14 00:27:10 2009 From: neelnatu at yahoo.com (Neelkanth Natu) Date: Tue Jul 14 00:27:21 2009 Subject: Diffs to fix ddb backtrace Message-ID: <681122.20462.qm@web34407.mail.mud.yahoo.com> Hi, This diff fixes a problem I encountered with ddb backtrace. The problem with looking for just 'j ra' instruction to find out the end of the previous function is that gcc does not emit that instruction for functions that are not supposed to return (for e.g. boot() or panic()). This is especially bad because the backtrace generated by calling panic() is unusable because boot() is right above panic() in the object file. This change looks for start of a function by looking for an instruction of the form: addiu sp,sp,- It so happens that gcc emits this as the first instruction for all functions that use the stack. We keep the 'j ra' method around for functions that don't use the stack. For e.g. here is backtrace output without the fix: mountroot> panic: Root mount failed, startup aborted. KDB: enter: panic [thread pid 1 tid 100001 ] Stopped at kdb_enter+0x50: lui at,0x8043 db> bt Tracing pid 1 tid 100001 td 0xc7847000 kdb_enter+50 (0,0,0,0) ra 80234d2c sz 24 80234378+9b4 (0,0,0,0) ra 803cbb98 sz 80 803a37b0+283e8 (0,0,0,0) ra 0 sz 0 pid 1 And this is the backtrace with the fix: mountroot> panic: Root mount failed, startup aborted. KDB: enter: panic [thread pid 1 tid 100001 ] Stopped at kdb_enter+0x50: lui at,0x8043 db> bt Tracing pid 1 tid 100001 td 0xc7847000 kdb_enter+50 (0,0,0,0) ra 80234d2c sz 24 panic+f8 (0,a,8059ffe4,0) ra 802be12c sz 40 vfs_mountroot+518 (0,a,8059ffe4,0) ra 801f1464 sz 96 801f13f0+74 (0,a,8059ffe4,0) ra 8020d338 sz 96 fork_exit+b0 (0,a,8059ffe4,0) ra 80395300 sz 40 fork_trampoline+10 (0,a,8059ffe4,0) ra 0 sz 0 pid 1 best Neel ==== //depot/user/neelnatu/projects_mips/src/sys/mips/mips/trap.c#1 - /amd/svlusr02.eng.netapp.com/vol/home24/neelnatu/p4/projects_mips/src/sys/mips/mips/trap.c ==== @@ -1229,7 +1229,25 @@ #if defined(DDB) || defined(DEBUG) -#define MIPS_JR_RA 0x03e00008 /* instruction code for jr ra */ +/* + * A function using a stack frame has the following instruction as the first + * one: addiu sp,sp,- + * + * We make use of this to detect starting address of a function. This works + * better than using 'j ra' instruction to signify end of the previous + * function (for e.g. functions like boot() or panic() do not actually + * emit a 'j ra' instruction). + * + * XXX the abi does not require that the addiu instruction be the first one. + */ +#define MIPS_START_OF_FUNCTION(ins) (((ins) & 0xffff8000) == 0x27bd8000) + +/* + * MIPS ABI 3.0 requires that all functions return using the 'j ra' instruction + * + * XXX gcc doesn't do this true for functions with __noreturn__ attribute. + */ +#define MIPS_END_OF_FUNCTION(ins) ((ins) == 0x03e00008) /* forward */ char *fn_name(unsigned addr); @@ -1326,9 +1344,21 @@ */ if (!subr) { va = pc - sizeof(int); - while ((instr = kdbpeek((int *)va)) != MIPS_JR_RA) + while (1) { + instr = kdbpeek((int *)va); + + if (MIPS_START_OF_FUNCTION(instr)) + break; + + if (MIPS_END_OF_FUNCTION(instr)) { + /* skip over branch-delay slot instruction */ + va += 2 * sizeof(int); + break; + } + va -= sizeof(int); - va += 2 * sizeof(int); /* skip back over branch & delay slot */ + } + /* skip over nulls which might separate .o files */ while ((instr = kdbpeek((int *)va)) == 0) va += sizeof(int); From invitations at boxbe.com Tue Jul 14 13:20:54 2009 From: invitations at boxbe.com (Mario Augusto Mania) Date: Tue Jul 14 13:21:00 2009 Subject: Mario Augusto Mania wants to share approved contacts Message-ID: <1717777386.12728973.1247577653399.JavaMail.prod@app002.boxbe.com> Skipped content of type multipart/related From dnyce at pilgrimtours.us Wed Jul 15 20:16:22 2009 From: dnyce at pilgrimtours.us (Pilgrim Tours) Date: Wed Jul 15 20:16:52 2009 Subject: Fund Raising Programs Message-ID: <20090715201621.07F3B8FC3B@mx1.freebsd.org> Dear Group Planner, A group sponsored event can be planned and promoted with very little work and practically no expense on your part. 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Example Itineraries Below: Florence & Venice Spring Tour Cohosted or Private Tours $1799.00 per person double (commission - $180) http://pilgrimtours.com/alumni/tours/FlorenceVenice.htm Egypt & Optional Nile Cruise Many Dates in 2010 $1298.00 per person double (commission - $130) Price Includes: Round trip airfare, 6 nights 4 star accommodations (buffet breakfast included), tour of Cairo, Egypt Museum, welcome and farewell dinners, roundtrip airport transfers. http://www.pilgrimtours.com/alumni/tours/cairo8.htm Spain Winter Break - First Class January 5-12, 2010 Other dates available. $1711.00 per person double (commission - $170) Price Includes: Round trip airfare, 6 nights first class accommodations (buffet breakfast included), tour of Malaga, welcome and farewell dinners, roundtrip airport transfers, morning tour of Malaga. http://www.pilgrimtours.com/broadcast/Alumni/Madrid_Malaga.htm Rome Winter Break January 5-12, 2010 Many dates available. $1469.00 per person double (commission - $150) Price Includes: Roundtrip air, air taxes, 6 night's accommodations at the Beverly Hills Hotel (superior 4 star property), American breakfast daily, welcome and farewell dinners, roundtrip private airport transfers in Rome, full day tour of Rome. Optional excursions: Florence, Pompeii, Ostia Antica, theatre. http://www.pilgrimtours.com/alumni/tours/villanovarome.htm Athens Winter Break January 5-12, 2010 Many dates available. $1498.00 per person double (commission - $150) Price Includes: Roundtrip air (bulk rates available nation-wide), air taxes, 6 night's accommodations (superior 4 star property), American breakfast daily, welcome and farewell dinners, roundtrip private airport transfers in Athens, day tour of Athens. Optional excursions: Islands day-cruise, Delphi, Cape Sounion, Mycenae, Athen Museums. http://www.pilgrimtours.com/alumni/tours/athens8.htm Winter in Southern Spain - Tourist Class November 2009 - March 2010 A GREAT VALUE!! $1393.00 per person double (commission - $140) Price Includes: Round trip airfare, 6 nights accommodations at Villa Turistica de Priego (buffet breakfast included), 4 dinners at the hotel, 1 dinner at a local restaurant in Sevilla, 1 lunch at a local restaurant in Cordoba, Flamenco show in Sevilla, all sightseeing. http://www.pilgrimtours.com/alumni/tours/SouthernSpain.htm China Beijing Adventure March 23-30, 2010 Many dates available. $1849.00 per person double (commission - $185) Price Includes: Airfare from Chicago and NYC, first class lodging for 6 nights, 6 breakfasts, 1 lunch and 1 dinner, touring as appears on itinerary. http://www.pilgrimtours.com/alumni/tours/chinaBeijing.htm Peru and Amazon Adventure February 16-26, 2010 Many dates available. $2585.00 per person double (commission - $260) Price Includes: Roundtrip airfare from JFK, hotel first class accommodations, breakfast, lunch and dinner daily, full time tour manager, sightseeing and admissions per itinerary, deluxe motorcoach transportation, air taxes, baggage handling, taxes, hotel fees, and meal gratuities. http://www.pilgrimtours.com/alumni/tours/Peru.htm Many Tour & Cruise Destinations Greece, Turkey, Italy, France, Malta, Sicily, Israel, Jordan, Egypt, British Isles, France, Germany, Switzerland, Scandinavia, Central & E. Europe, Morocco, Tunisia, South Africa, Latin America, Mexico, Hawaii and many tours in the USA & Canada. 8 Day Packages - Less then $1600: Pilgrim has numerous one week programs including meals, lodging, great sightseeing options for under $1600! SALES MANAGER - TIM NYCE Pilgrim has much to offer! You have the opportunity to travel on prospective alumni programs at below our cost, free web page construction, generous commissions, mail and advertising contribution, color brochures, posters, post cards, plus the security of error & omission insurance with guaranteed departures and no minimum numbers. Information: 800.322.0788 ext. 105 tnyce@pilgrimtours.com This email was sent to freebsd-mips@freebsd.org, by Pilgrim Tours http://www.pilgrimtours.com P O Box 268 3821 Main Street Morgantown, PA 19543 United States If you do not wish to receive future e-mail from Pilgrim Tours, please use the link below. http://rm.resultsmail.com/unsubscribe.cfm?uid=c5dea179-6b8c-4372-9150-5182dc99db90&mid=4e8c8078-002e-4479-bc30-9694b29d2ea2&route=http%3A%2F%2Frm%2Eresultsmail%2Ecom%2Funsubscribed%2Ecfm Powered by ResultsMail (http://www.resultsmail.com/) ResultsMail Privacy Policy: http://www.resultsmail.com/privacy ResultsMail Permission Email Policy: http://www.resultsmail.com/permission From neelnatu at yahoo.com Thu Jul 16 04:57:53 2009 From: neelnatu at yahoo.com (Neelkanth Natu) Date: Thu Jul 16 04:57:59 2009 Subject: buildworld, installworld and multiuser on Sibyte Message-ID: <437476.38747.qm@web34408.mail.mud.yahoo.com> Hi, After a long time trying to get this to work I was finally able to do a buildworld, installworld and boot multiuser on the Sibyte reference platform. I was sidetracked by two issues: - I had one bad dimm that was causing cache error exceptions - I was booting with more memory that can be mapped by KSEG0 - it seems that the pmap code doesn't support this Anyways, this is a milestone for the SWARM platform and I thought I would share it with the list. best Neel From info at omegaworldclass.org Wed Jul 29 21:52:55 2009 From: info at omegaworldclass.org (Customer Insights) Date: Wed Jul 29 21:53:49 2009 Subject: 'Mastering Customer Insights & Superior Marketing Strategies" Workshop 2009, 2 September @ Conrad Hotel, Bangkok Message-ID: <20090730045244.416770843@omegaworldclass.org> From gonzo at freebsd.org Thu Jul 30 23:50:30 2009 From: gonzo at freebsd.org (Oleksandr Tymoshenko) Date: Thu Jul 30 23:50:37 2009 Subject: Diffs to fix ddb backtrace In-Reply-To: <681122.20462.qm@web34407.mail.mud.yahoo.com> References: <681122.20462.qm@web34407.mail.mud.yahoo.com> Message-ID: <4A7231BE.3090703@freebsd.org> Neelkanth Natu wrote: > Hi, > > This diff fixes a problem I encountered with ddb backtrace. > > The problem with looking for just 'j ra' instruction to find out the > end of the previous function is that gcc does not emit that > instruction for functions that are not supposed to return (for e.g. > boot() or panic()). This is especially bad because the backtrace > generated by calling panic() is unusable because boot() is right > above panic() in the object file. > > This change looks for start of a function by looking for an instruction > of the form: addiu sp,sp,- > > It so happens that gcc emits this as the first instruction for all > functions that use the stack. We keep the 'j ra' method around for > functions that don't use the stack. Thanks! This is something I've always wanted to do but never did :) commited to projects/mips From neelnatu at yahoo.com Fri Jul 31 00:51:53 2009 From: neelnatu at yahoo.com (Neelkanth Natu) Date: Fri Jul 31 00:51:59 2009 Subject: Diffs to fix L1 cache flush problems Message-ID: <153254.15259.qm@web34402.mail.mud.yahoo.com> Hi, This is a simple change that fixes problems invalidating L1 data/instruction caches. The problem is that the type of the variable that holds the size of the instruction/data caches is uint8_t. Clearly this is going to overflow. On the Sibyte with 32KB cache size the uint8_t was causing it to be truncated to 0. This in turn makes the cache flush routines turn into no-ops. I ran into this when testing kernel loadable modules and have verified that this change fixes the problem. best Neel ==== //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/include/cpuinfo.h#2 (text) - //depot/user/neelnatu/freebsd_sibyte/src/sys/mips/include/cpuinfo.h#3 (text) ==== content @@ -57,11 +57,11 @@ u_int16_t tlb_nentries; u_int8_t icache_virtual; struct { - u_int8_t ic_size; + unsigned int ic_size; u_int8_t ic_linesize; u_int8_t ic_nways; u_int16_t ic_nsets; - u_int8_t dc_size; + unsigned int dc_size; u_int8_t dc_linesize; u_int8_t dc_nways; u_int16_t dc_nsets;