TR usage in the kernel
Arun Sharma
arun.sharma at intel.com
Fri Jul 2 16:19:30 PDT 2004
Currently, loader.efi and the kernel seem to be using 256MB TRs to map both text and data
from:
0xe000000000000000 - 0xe000000000000000+256MB
This is problematic for two reasons:
1. Attribute aliasing (cacheable and uncacheable memory being mapped by the same TLB entry)
2. Since it starts mapping at low memory (physical address 0), the likelyhood of running into (1) is high.
The safe TR size can be determined only after parsing the EFI map. Might be safer to use a small TR in the absence of this information. Also, avoiding low memory may be a good idea.
-Arun
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