i386/126525: Extended PCI Configuration register (>= 0x100) not enabled on some Intel 915 based platforms

[Arthur Hartwig]

>Number:         126525
>Category:       i386
>Synopsis:       Extended PCI Configuration register (>= 0x100) not enabled on some Intel 915 based platforms
>Confidential:   no
>Severity:       non-critical
>Priority:       medium
>Responsible:    freebsd-i386
>State:          open
>Quarter:        
>Keywords:       
>Date-Required:
>Class:          sw-bug
>Submitter-Id:   current-users
>Arrival-Date:   Thu Aug 14 05:40:01 UTC 2008
>Closed-Date:
>Last-Modified:
>Originator:     Arthur Hartwig
>Release:        7.0
>Organization:
Nokia
>Environment:
>Description:
Access to extended PCI Configuration registers (0x100 and above on PCI Express devices) is not enabled on some platforms based on the Intel 915 chipset nor on platforms based on the Intel 5000 chipsets.



>How-To-Repeat:

>Fix:
In sys/i386/pci/pci_cfgreg.c change pci_cfgregopen to read:

/* 
 * Initialise access to PCI configuration space 
 */
int
pci_cfgregopen(void)
{
	static int		opened = 0;
	u_int16_t		vid, did;
	u_int16_t		v;

	if (opened)
		return(1);

	if (pcireg_cfgopen() == 0)
		return(0);

	v = pcibios_get_version();
	if (v > 0)
		PRVERB(("pcibios: BIOS version %x.%02x\n", (v & 0xff00) >> 8,
		    v & 0xff));
	mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
	opened = 1;

	/* $PIR requires PCI BIOS 2.10 or greater. */
	if (v >= 0x0210)
		pci_pir_open();

	/*
	 * Grope around in the PCI config space to see if this is a
	 * chipset that is capable of doing memory-mapped config cycles.
	 * This also implies that it can do PCIe extended config cycles.
	 */

	vid = pci_cfgregread(0, 0, 0, PCIR_VENDOR, 2);
	did = pci_cfgregread(0, 0, 0, PCIR_DEVICE, 2);
	if (vid == 0x8086) {
		switch (did) {
		case 0x3590:
		case 0x3592:
			/* Intel 7520 or 7320 */
			pciebar = pci_cfgregread(0, 0, 0, 0xce, 2) << 16;
			pciereg_cfgopen();
			break;

		case 0x2580:
		case 0x2584:
		case 0x2590:
			/* Intel 915, 925, 915GM/PM/GMS/GME or 910GML/GMLE */
			pciebar = pci_cfgregread(0, 0, 0, 0x48, 4);
			pciereg_cfgopen();
			break;
		
		case 0x25d8:
		case 0x25d0: 
		case 0x25d4:
			/* Intel 5000P/Z/V */
			pciebar = pci_cfgregread(0, 16, 0, 0x64, 4);
#ifndef PAE
			if (pciebar >= 0x10000) {
				printf("%s: Memory mapped PCI configuration "
				       "area base 0x%08x too high\n", 
				       __FUNCTION__, pciebar
);
				pciebar = 0;
				break;
			}
#endif
			pciebar = pciebar << 16;
			pciereg_cfgopen();
			break;
		}
	}

	return(1);
}




>Release-Note:
>Audit-Trail:
>Unformatted: