IRQ31 and IRQ32 on HPDL585 running FreeBSD 7.0 are consuming
HIGH CPU usage
Won De Erick
won.derick at yahoo.com
Fri Nov 14 00:48:50 PST 2008
> ----- Original Message ----
> From: John Baldwin <jhb at freebsd.org>
> To: freebsd-hardware at freebsd.org
> Cc: Jeremy Chadwick <koitsu at freebsd.org>; Won De Erick <won.derick at yahoo.com>
> Sent: Friday, November 14, 2008 3:38:25 AM
> Subject: Re: IRQ31 and IRQ32 on HPDL585 running FreeBSD 7.0 are consuming HIGH CPU usage
> On Thursday 13 November 2008 03:19:36 am Jeremy Chadwick wrote:
> > On Thu, Nov 13, 2008 at 12:07:37AM -0800, Won De Erick wrote:
> > > Noted on this, I will update you through this thread.
> > >
> > > However is there any possibility of the following:
> > >
> > > > I don't know if there's a way to split the interrupt request for each
bce's Rx and Tx,
> > > > which means a total of four IRQs, and eventually four cores (or 4 CPUs)
> > > > for the transactions. With this way, the IDLE processors would be
> > >
> > > What I mean here is, for the two interfaces:
> > >
> > > one IRQ for bce0 Rx
> > > one IRQ for bce0 Tx
> > > one IRQ for bce1 Rx
> > > one IRQ for bce1 Tx
> > I can't even begin to imagine how this would be possible on any NIC.
> igb(4) does it. It is quite possible and one of the purposes of MSI.
> However, the current bce(4) hardware does not support this. It only allows
> for a single message and thus a single IRQ per-device.
based from the man pages, igb driver supports Intel NICs w/ controllers starting from Intel NIC controller 82574.
One Intel NIC (controller: 82576, see http://www.intel.com/Assets/PDF/prodbrief/320116.pdf) says it supports MSIX which minimizes the overhead of interrupts and allows load balancing of interrupt handling between multiple cores/CPUs.
I should want a little more explanation how this feature being handled by MSIX. Thanks a lot.
> John Baldwin
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