wired memory - again!

[Konstantin Belousov]

On Wed, Jun 13, 2012 at 07:14:09AM -0600, Ian Lepore wrote:
> On Tue, 2012-06-12 at 23:45 +0300, Konstantin Belousov wrote:
> > On Tue, Jun 12, 2012 at 08:51:34AM -0600, Ian Lepore wrote:
> > > On Sat, 2012-06-09 at 22:45 +0200, Wojciech Puchar wrote:
> > > > >
> > > > > First, all memory allocated by UMA and consequently malloc(9) is
> > > > > wired. In other words, almost all memory used by kernel is accounted
> > > > > as wired.
> > > > >
> > > > yes i understand this. still i found no way how to find out what allocated 
> > > > that much.
> > > > 
> > > > 
> > > > > Second, the buffer cache wires the pages which are inserted into VMIO
> > > > > buffers. So your observation is basically right, cached buffers means
> > > > 
> > > > what are exactly "VMIO" buffers. i understand that page must be wired WHEN 
> > > > doing I/O.
> > > > But i have too much wired memory even when doing no I/O at all.
> > > 
> > > I agree, this is The Big Question for me.  Why does the system keep
> > > wired writable mappings of the buffers in kva after the IO operations
> > > are completed?  
> > Read about buffer cache, e.g. in the Design and Implementation of
> > the FreeBSD OS book.
> > 
> > > 
> > > If it did not do so, it would fix the instruction-cache-disabled bug
> > > that kills performance on VIVT cache architectures (arm and mips) and it
> > > would reduce the amount of wired memory (that apparently doesn't need to
> > > be wired, unless I've missed the implications of a previous reply in
> > > this thread).
> > 
> > I have no idea what is the bug you are talking about. If my guess is
> > right, and it specifically references unability of some processors
> > to correctly handle several mappings of the same physical page into
> > different virtual addresses due to cache tagging using virtual address
> > instead of physical, then this is a hardware bug, not software.
> > 
> 
> This bug:
> 
> http://lists.freebsd.org/pipermail/freebsd-arm/2012-January/003288.html
> 
> The bug isn't the VIVT cache hardware, it's the fact that the way we
> handle the requirements of the hardware has the side effect of leaving
> the instruction cache bit disabled on executable pages because the
> kernel keeps writable mappings of the pages even after the IO is done.
Can you point me at the exact code in arm pmap ?

I remember an issue on PPC which Nathan discussed, that sounds somewhat
similar (but I still do not understand what exactly happens on ARM). On
PowerPC, icache needs to be explicitely flushed if write happen to the
executable mapping. See r233949 for current solution. There were some
followups, but I believe the core change is still valid.

> 
> > AFAIR, at least HP PA and MIPS have different instantiation of this problem.
> > Our kernel uses multi-mapping quite often, and buffers is only one example.
> > 
> > Also, why do you think that the pages entered into buffers shall not be
> > wired, it is completely beyond my understanding.
> 
> What's beyond my understanding is why a page has to remain wired after
> the IO is complete.  That question seems to me to be tangentially
> related to the above question of why the kernel needs to keep a writable
> mapping of the buffer after it's done writing into the page (either via
> DMA or via uiomove() depending on the direction of the IO).

Because the buffer is cached.
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