intel checksum offload
lacombar at gmail.com
Sun Sep 18 19:19:48 UTC 2011
On Sat, Sep 17, 2011 at 4:32 PM, YongHyeon PYUN <pyunyh at gmail.com> wrote:
> On Sat, Sep 17, 2011 at 11:57:10AM +0430, Hooman Fazaeli wrote:
>> Hi list,
>> The data sheet for intel 82576 advertises IP TX/RX checksum offload
>> but the driver does not set CSUM_IP in ifp->if_hwassist. Does this mean that
>> driver (and chip) do not support IP TX checksum offload or the support for
>> TX is not yet included in the driver?
> After reading this mail, I checked em(4)/lem(4) code and noticed
> these drivers removed CSUM_IP capability as well. igb(4) didn't
> support CSUM_IP from day 1 but em(4)/lem(4) used to take advantage
> of IP checksum offloading capability.
> Given that these drivers share many code with Linux, Jack may know
> the details and why IP checksum offloading code was removed. Note,
> Linux does not use IP checksum offloading so I guess this could be
> oversight in shared code.
> BTW, hackers may not be right ML to post this kind of post.
> CCed to jfv@, the driver maintainer.
This is slightly off-topic, but still..
FWIW, I'm not really impressed by what chips claim to support vs. what
has been implemented in the driver. As per the product brief, the
82574 supports multiqueue (at least should support up to 5 MSI-X
vectors, 2 RX and 2 TX), but this support was removed from em(4) in
mid-2010. Also, the 82571 and the 82574 should also support header
split, but this is currently only implemented in igb(4), not em(4).
: the commit message say "performance was not good", but it is not
the driver's developer to decide whether or not a feature is good or
not. The developer's job is to implement the chip capabilities, and
let it to the user to enable or disable the capabilities. At best, the
developer can decide whether or not to enable the feature by default.
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