multiple interrupts between cli and sti

[Erich Dollansky]

Hi,

Andriy Gapon wrote:

I cannot tell you if this is still the same for modern designs.

> ... -> iret -> interrupted again

This was the behaviour earlier.
> 
> Is this a deterministic behavior ? Or some timings are at play?

The PIC should never release the Interrupt signal to the CPU as long as 
a single interrupt is not serviced.

But the 8259 can be programmed to trigger via level or slope.

So, this behaviour is only seen when level triggering is used.

As I said at the bginning, I do not know how current designs handle it.

Erich