Weird PCI interrupt delivery problem (resolution, sort of)

[Craig Boston]

On Wed, Jan 25, 2006 at 08:04:07AM -0700, Scott Long wrote:
> Either that, or the read imposes enough delay to let whatever was
> happening during the DELAY call work.   I find it hard to believe that
> uncached writes would get delayed like this.  I've lost the original
> posting on this, could you provide the dmesg and computer make/model
> again?

It's a Toshiba Satellite L25-S1192.  The chipset is ATI Radeon Xpress
200M (RS480).

Verbose dmesgs are up at http://www.gank.org/freebsd/l25

acpi+apic.txt is a 6.0-RELEASE GENERIC kernel (before I upgraded the
memory, but the APIC thing is independent of that)

apic2.txt is a verbose dmesg with my current kernel (stock 6.0-STABLE +
read-after-write change to local_apic.c).

Craig