Atomic operations across multiple processors

[Peter Jeremy]

atomic(9) states:
 The current set of atomic operations do not necessarily guarantee atomic-
 ity across multiple processors.  ...  On the i386 architecture, the cache
 coherency model requires that the hardware perform this task, thus the
 atomic operations are atomic across multiple processors.  On the ia64
 architecture, coherency is only guaranteed for pages that are configured
 to using a caching policy of either uncached or write back.

Unfortunately, this doesn't document the behaviour for other
architectures - this makes it difficult to write portable code.

For the ia64, the statement isn't especially helpful because there's
no indication of what caching policy is used by default and how to
change it.  Also, it seems odd that write-back pages would be coherent
whilst write-through pages aren't - is this a typo?  The man page is
also inconsistent with /sys/ia64/include/atomic.h which states that
atomic operations _are_ SMP safe.

I've tried looking at the mutex code to see how the iA64 achieves
inter-processor synchronisation on top of (supposedly) non-
synchronised atomic(9) primitives but can't find anything.

I'd appreciate comments from people familiar with non-iA32 architectures.

-- 
Peter Jeremy