Determining CPU features / cache organization from userland

[Bruce M Simpson]

On Sat, Oct 11, 2003 at 01:58:27PM +1000, Peter Jeremy wrote:
> >If you do this,  it may make sense to use the same names as MacOSX.
> 
> What if your hardware has different linesizes for different caches?

I noticed whilst peering in Apple Developer Notes that G5 has 128 byte
cache line size, and this screws up mutexes bigtime. (!!)

OS X definitions considered too PowerPC centric. I think the best way
to handle all cases is thus:-

 - Support 3 levels of cache.
 - Each level may be unified or split between code and data
   not-quite-Von-Neumann-style.
 - Allow explicit retrieval of this info keyed on the cache you're
   interested in. This means: hw.cache.lN.(linesize|lines|sets)
 - Do similar for the TLB insofar as we can return information about
   the chip's TLB. I know for example from talking to peter@ that
   the Opteron is quite a different beast (ASNs, flush filter, etc).
 - Assume that all CPUs have identical characteristics in an SMP system.
   Trying to assume otherwise is pointless. People should be using matched
   chips anyway.

BMS