Loss of ed(4) in a RC1 booted in qemu

M. Warner Losh imp at bsdimp.com
Thu Oct 13 16:27:45 PDT 2005

In message: <20051013200254.GA11267 at saturn.kn-bremen.de>
            Juergen Lock <nox at jelal.kn-bremen.de> writes:
: On Thu, Oct 13, 2005 at 02:28:18PM -0400, Jung-uk Kim wrote:
: > On Thursday 13 October 2005 12:10 pm, Jung-uk Kim wrote:
: > > QEMU emulates RTL8029:
: > >
: > > ed0: <RealTek 8029> port 0xc100-0xc1ff irq 11 at device 3.0 on pci0
: > > ed0: Reserved 0x100 bytes for rid 0x10 type 4 at 0xc100
: > >
: > > and Warner Losh MFC'd new ed(4) right before 6.0-RC1:
: > >
: > > http://docs.freebsd.org/cgi/mid.cgi?200510081800.j98I0fRI089493
: > >
: > > The new driver does more aggressive probing and it seems QEMU
: > > cannot handle it.
: > 
: > Just for the time being, you can drop the attachment in 
: > ports/emulators/qemu/files directory and rebuild qemu to get ed(4) 
: > back.
: > 
: > Jung-uk Kim
: >[patch snipped]
: Okay, we could add this as an option to our qemu port (`-ne2kvia' or
: something like that), anyone thinks it is necessary?  (I guess this
: issue will be fixed in 6.0-R?)

I've committed patches to -current to fix this problem.  The fixes
correct a minor botch in the probing code, while also adding tolerance
for the RTL8029 that's claimed to be there to not really be there.
I've posted patches to qemu that improves that RTL8029 emulation, but
those aren't required for FreeBSD to work.  RC1 won't work with qemu,
patched or unpatched, due to the minor botch.  RC2 and newer will have
this problem fixed.  The qemu folks can include and improve upon my
patches as they see fit in the future.

The problem with just switching to the VIA VT86C926 is that it isn't
exactly like a NE-2000.  According to its datasheet:

>>VT86C926 supports the control and status registers of DP8390 except
>>those explained as follows.
>> * VT86C926 supports all page 1 registers. Only part of Page 2 is
>>   supported.
>> * VT86C926 supports Early Transmit Underrun (ETUN)
>> * VT86C926 supports most of page 0 registers.
>> * The meaning and use of 01H (CLAD0) and 02H (CLAD1) of page 0 is
>>   altered.
>> * The 06H (FIFO port) of page 0 is not supported.
>> * The following control/status bits in page 0 are not supported:
>>   -- (D3,D4,D5) == (0,1,1) of CR (00H) : Send Packet Command (RD0 - RD2)
>>   -- D1 of DCR: Byte Order Select (BOS)
>>   -- D2 of DCR: Long Address Select (LAS)
>>   -- D4 of DCR: Auto-initialize Remote (ARM)
>>   -- D5, D6 of DCR: FIFO Threshold Select (FT0 and FT1)
>>   -- D4 of TCR: Collision Offset Enable (OFST)
>>   -- D5 of TSR: FIFO Underrun (FU)
>>   -- D7 of TSR: Out of Window Collision (OWC)
>>   -- D3 of RSR: FIFO Overrun (FO)

None of which are enshrined in hw/ne2000.c as far as I can tell.  The
early interrupt stuff isn't part of a NE2000 at all (that's the
ETUN).  Of course its datasheet is maddening.  It talks about
different bits and registers, but never defines their offsets or


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