TL-WR1043: switch

[Adrian Chadd]

On 13 December 2011 02:03, Stefan Bethke <stb at lassitu.de> wrote:

>> Ok. So what's arge0's PHY configuration coming from? Or is it being
>> handled as a multi-phy, where it forces speed/duplex (and MAC PLL +
>> MII clock but I have to fix that for ar71xx/ar724x) and then just
>> nails the port as always up, rather than binding a phy instance to it?
>
> It's hard-wired on both ends, the PHY MAC and the arge MAC.

Ok. I'll have to review this a bit further, along with ray's switch
interface work. Hopefully we can tidy up something and get it into
-HEAD.

The trouble ray is having at the moment is where the switch PHY hangs
off of arge1, rather than arge0. This means that arge0 gets probed and
has no PHY; then arge1 gets probed and has the switch PHY. I'd rather
(for now) just have arge0 be "hard" coded up to something and use the
switch API to configure the switch ports themselves. If that works
(well enough for now) then we can just get the switch code + drivers
into -HEAD and get it all polished.

Thanks for chasing this up! I really appreciate it.

FYI: I'm working on the GPIO stuff now. I'll try to get the rest of
the GPIO code changes into -HEAD by the weekend so we can use all the
GPIO lines on each of our boards, along with being able to override
the GPIO function register.


Adrian