NAND Flash Framework for review
andrew at fubar.geek.nz
Tue Mar 16 01:10:49 UTC 2010
On Mon, 15 Mar 2010 12:14:31 +0100
Grzegorz Bernacki <gjb at semihalf.com> wrote:
> >> Chip drivers:
> >> - lnand and snand have magic numbers to figure out which drive to
> >> use. We should move these to a flag in the chip parameters.
> > We just need to add the chip size in nand_params and based on that
> > we can calculate the number of address cycles (see below) and the
> > type of chip (if chip >= 128MB and pagesize > 512 then you have a
> > large page device).
> Yes, I was thinking about adding size of page and column address to
> parameters of nfc_send_address.
Why not just send each address byte separately like when the command is
sent? This will then push the requirement to know how many address
bytes to the chip driver.
> >> - nand_read_pages should be a device method so we can customise
> >> how we handle reading of pages.
> By customising you mean, using interlea
Yes. I have also seen some interesting ways of connecting NAND flash. I
would like to allow the developers to handle these by overriding the
KOBJ methods as required.
> >> Ideas:
> >> - Can we move ecc and bbt handling into GEOM? This will allow us to
> >> bypass them when required.
> > This is a mandatory feature (disable ecc and may be the bbt checks)
> > if you need to deal with some kind of unknown nand FS or unknown
> > nand oob layout (like make a backup of your unknown nand data
> > before erase it).
> Ok, I didn't know that disabling ECC and BBT is so important. Let me
> think about moving it to geom layer.
It is also important for filesystems that have their own ECC handling
code, e.g. YAFFS expects to manage the OOB it's self including the ECC.
I'm not sure how it expects to handle the BBT.
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