Need a clarification regarding I2C bus frequency in FreeBSD

[Daniel Braniss]

> On 19 Aug 2018, at 21:21, Ian Lepore <ian at freebsd.org> wrote:
> 
> On Sun, 2018-08-19 at 19:23 +0530, Rajesh Kumar wrote:
>> Hi Ian,
>> 
>> Basically, I want to set the I2C clock frequency for Designware IP in our
>> board to 150Mhz.  So, I was looking for the way in FreeBSD.
>> 
>> So, Is this the frequency which is configured through the clock high/low
>> registers? I see the those register are coded to 100 and 125 currently, I
>> am not sure how that value is arrived. If it needs to be configured for
>> 150Mhz, how to derive the appropriate values? I looked at the DW_apb_i2c
>> databook section 3.11 to understand about it.  I am still unclear.  I see a
>> comment saying "Program based on 25000 Hz clock". In my case, should they
>> be programmed based on 150Mhz clock?
> 
> Rajesh,
> 
> Please bottom-post when replying on freebsd mailing lists, mixed top-
> and bottom-posting is too confusing.
> 
> What exactly do you mean when you say "the i2c clock frequency"?
> 
> The datasheet appears to use a term like that to refer to the internal
> clock used to drive the IP block in the chip. That base clock is then
> divided down to create the i2c bus frequency on the I2C_SCL line.
> 
> The IG4_REG_SS_SCL_HCNT and IG4_REG_SS_SCL_LCNT registers are the
> duration in base clock ticks that the SCL line is held high and low for
> standard speed. The registers with FS in the name are for high speed
> mode.
> 
> The comment block and the values our driver programs into those
> registers appear to be wildly wrong. There is no way a base clock
> running at 25KHz can be divided down to create i2c bus speeds of 100KHz
> and 400KHz for standard and fast modes. If the base clock really is
> 25KHz then the driver currently sets the i2c bus to run at 111Hz.
> 
> The hardware default values for the HCNT/LCNT registers, as given in
> the datasheet referenced by the driver [1], would be consistant with an
> internal base clock speed of 1GHz. The fact that the header file
> defines a IG4_REG_CLK_PARMS register, but the datasheet doesn't mention
> it, makes me think that on some versions of the hardware the speed is
> fixed and the driver has to know what that is based on the version, or
> vendor, or something. Other versions of the hardware may have
> information about the base clock speed in that IG4_REG_CLK_PARMS
> register.
> 
> What we need is for someone who has this hardware to put an
> oscilliscope on the SCL line and get us some real-world truth.
> 
> [1] http://www.intel.com/content/www/us/en/processors/core/4th-gen-core-family-mobile-i-o-datasheet.html?wapkw=datasheets+4th+generation <http://www.intel.com/content/www/us/en/processors/core/4th-gen-core-family-mobile-i-o-datasheet.html?wapkw=datasheets+4th+generation>
> 
> -- Ian


hi,
I have similar issues with the allwinner/twsi but I do have a Saleae Logic and here is a nice picture:



danny