memory barriers in bus_dmamap_sync() ?

[Adrian Chadd]

On 10 January 2012 13:37, Luigi Rizzo <rizzo at iet.unipi.it> wrote:
> I was glancing through manpages and implementations of bus_dma(9)
> and i am a bit unclear on what this API (in particular, bus_dmamap_sync() )
> does in terms of memory barriers.
>
> I see that the x86/amd64 and ia64 code only does the bounce buffers.
> The mips seems to do some coherency-related calls.
>
> How do we guarantee, say, that a recently built packet is
> to memory before issuing the tx command to the NIC ?

The drivers should be good examples of doing the right thing. You just
do pre-map and post-map calls as appropriate.

Some devices don't bother with this on register accesses and this is a
bug. (eg, ath/ath_hal.) Others (eg iwn) do explicit flushes where
needed.


Adrian