AHCI on ICH7

Michael Butler imb at protected-networks.net
Wed Jan 12 15:54:15 UTC 2011


On 01/12/11 10:44, Alexander Motin wrote:

 [ .. snip .. ]

> PCIR_BAR(5) is not set in this case, only 0-4. It won't help.

Ugh! My bad .. the only other option is to adjust the entry in ahci.c
for that chip-id, find a suitably "free" memory window and do something
like the attached patch (set 'AHCI_MEM_HACK' to the base of whatever
window you can allocate).

I use this on a Toshiba A-105 laptop but, in the process, I lose the
ability to talk to the PATA DVD-drive (the reason why the manufacturer
set compatibility mode in the BIOS).

On the other hand it gets me the (huge!) benefits of NCQ ;-)

	imb
-------------- next part --------------
*** src/sys/dev/ahci/ahci.c	Sat May 22 12:07:12 2010
--- src/sys/dev/ahci/ahci.c-patched	Sat May 22 08:10:36 2010
***************
*** 129,134 ****
--- 129,135 ----
  	{0x26838086, 0x00, "Intel ESB2",	0},
  	{0x27c18086, 0x00, "Intel ICH7",	0},
  	{0x27c38086, 0x00, "Intel ICH7",	0},
+ 	{0x27c48086, 0x00, "Intel ICH7M",	0},
  	{0x27c58086, 0x00, "Intel ICH7M",	0},
  	{0x27c68086, 0x00, "Intel ICH7M",	0},
  	{0x28218086, 0x00, "Intel ICH8",	0},
***************
*** 324,334 ****
--- 325,353 ----
  	ctlr->quirks = ahci_ids[i].quirks;
  	resource_int_value(device_get_name(dev),
  	    device_get_unit(dev), "ccc", &ctlr->ccc);
+ 
+ #define AHCI_MEM_HACK 0xF0D44400	/* 0xf0d443ff is the last used by others on Toshiba A105 */
+ 
+ 	/* Need to set the SCRAE bit and ensure SCRD not set */
+ 	pci_write_config(dev, 0x94, (pci_read_config(dev, 0x94, 4) | 0x200) & ~0x4000, 4);
+ 	/* enable MSE */
+ 	pci_write_config(dev, 0x4, (pci_read_config(dev, 0x4, 2) | 2), 2);
+ 	pci_write_config(dev, 0x24, AHCI_MEM_HACK, 4);	
+ 	pci_write_config(dev, 0x90, 0x40, 1);	/* AHCI + non-combined */
+ 
+ 	/* allocate a free memory window for BAR(5) */
+ 	ctlr->r_rid = PCIR_BAR(5);
+ 	bus_set_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, AHCI_MEM_HACK, 0x400);
+ 
  	/* if we have a memory BAR(5) we are likely on an AHCI part */
  	ctlr->r_rid = PCIR_BAR(5);
  	if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
  	    &ctlr->r_rid, RF_ACTIVE)))
  		return ENXIO;
+ 
+ 	/* enable ICH7M ports in AHCI space */
+ 	ATA_OUTL(ctlr->r_mem, AHCI_PI, ATA_INL(ctlr->r_mem, AHCI_PI) | 5);
+ 
  	/* Setup our own memory management for channels. */
  	ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem);
  	ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem);


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