Call for testers: fxp(4) WOL

[Pyun YongHyeon]

I've implemented WOL for fxp(4) and it works ok to me. Because
there too many variants of fxp(4) hardwares I'd like to hear
success/failure report before committing attached patch to tree.
It seems that the following Intel 8255x supports WOL. Apparently
82557 lacks WOL capabillity.

82558
82559
82550
82551

If your suspend/resume works on your system you can also wake up
your system in suspend by WOL.

Thanks.
-- 
Regards,
Pyun YongHyeon
-------------- next part --------------
Index: sys/dev/fxp/if_fxp.c
===================================================================
--- sys/dev/fxp/if_fxp.c	(revision 183858)
+++ sys/dev/fxp/if_fxp.c	(working copy)
@@ -402,7 +402,7 @@
 	uint32_t val;
 	uint16_t data, myea[ETHER_ADDR_LEN / 2];
 	u_char eaddr[ETHER_ADDR_LEN];
-	int i, prefer_iomap;
+	int i, pmc, prefer_iomap;
 	int error;
 
 	error = 0;
@@ -480,6 +480,16 @@
 		sc->revision = pci_get_revid(dev);
 
 	/*
+	 * Check availability of WOL.
+	 */
+	if (sc->revision >= FXP_REV_82558_A4) {
+		fxp_read_eeprom(sc, &data, 10, 1);
+		if ((data & 0x20) != 0 &&
+		    pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0)
+			sc->flags |= FXP_FLAG_WOLCAP;
+	}
+
+	/*
 	 * Determine whether we must use the 503 serial interface.
 	 */
 	fxp_read_eeprom(sc, &data, 6, 1);
@@ -778,6 +788,11 @@
 		ifp->if_capenable |= IFCAP_HWCSUM;
 	}
 
+	if (sc->flags & FXP_FLAG_WOLCAP) {
+		ifp->if_capabilities |= IFCAP_WOL_MAGIC;
+		ifp->if_capenable |= IFCAP_WOL_MAGIC;
+	}
+
 #ifdef DEVICE_POLLING
 	/* Inform the world we support polling. */
 	ifp->if_capabilities |= IFCAP_POLLING;
@@ -938,17 +953,13 @@
 static int
 fxp_shutdown(device_t dev)
 {
-	struct fxp_softc *sc = device_get_softc(dev);
 
 	/*
 	 * Make sure that DMA is disabled prior to reboot. Not doing
 	 * do could allow DMA to corrupt kernel memory during the
 	 * reboot before the driver initializes.
 	 */
-	FXP_LOCK(sc);
-	fxp_stop(sc);
-	FXP_UNLOCK(sc);
-	return (0);
+	return (fxp_suspend(dev));
 }
 
 /*
@@ -960,11 +971,26 @@
 fxp_suspend(device_t dev)
 {
 	struct fxp_softc *sc = device_get_softc(dev);
+	struct ifnet *ifp;
+	int pmc;
+	uint16_t pmstat;
 
 	FXP_LOCK(sc);
 
+	ifp = sc->ifp;
+	if (pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) {
+		pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
+		pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
+		if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
+			/* Request PME. */
+			pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
+			sc->flags |= FXP_FLAG_WOL;
+			/* Reconfigure hardware to accept magic frames. */
+			fxp_init_body(sc);
+		}
+		pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
+	}
 	fxp_stop(sc);
-	
 	sc->suspended = 1;
 
 	FXP_UNLOCK(sc);
@@ -980,9 +1006,23 @@
 {
 	struct fxp_softc *sc = device_get_softc(dev);
 	struct ifnet *ifp = sc->ifp;
+	int pmc;
+	uint16_t pmstat;
 
 	FXP_LOCK(sc);
 
+	if (pci_find_extcap(sc->dev, PCIY_PMG, &pmc) == 0) {
+		sc->flags &= ~FXP_FLAG_WOL;
+		pmstat = pci_read_config(sc->dev, pmc + PCIR_POWER_STATUS, 2);
+		/* Disable PME and clear PME status. */
+		pmstat &= ~PCIM_PSTAT_PMEENABLE;
+		pci_write_config(sc->dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
+		if ((sc->flags & FXP_FLAG_WOL) != 0) {
+			/* Clear wakeup events. */
+			CSR_READ_1(sc, FXP_CSR_PMDR);
+		}
+	}
+
 	CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
 	DELAY(10);
 
@@ -2047,8 +2087,7 @@
 	cbp->rcv_crc_xfer =	0;	/* (don't) xfer CRC to host */
 	cbp->long_rx_en =	sc->flags & FXP_FLAG_LONG_PKT_EN ? 1 : 0;
 	cbp->ia_wake_en =	0;	/* (don't) wake up on address match */
-	cbp->magic_pkt_dis =	0;	/* (don't) disable magic packet */
-					/* must set wake_en in PMCSR also */
+	cbp->magic_pkt_dis =	sc->flags & FXP_FLAG_WOL ? 0 : 1;
 	cbp->force_fdx =	0;	/* (don't) force full duplex */
 	cbp->fdx_pin_en =	1;	/* (enable) FDX# pin */
 	cbp->multi_ia =		0;	/* (don't) accept multiple IAs */
@@ -2458,6 +2497,10 @@
 			}
 		}
 #endif
+		if ((mask & IFCAP_WOL_MAGIC) != 0 &&
+		    (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
+			ifp->if_capenable ^= IFCAP_WOL_MAGIC;
+
 		if (mask & IFCAP_VLAN_MTU) {
 			FXP_LOCK(sc);
 			ifp->if_capenable ^= IFCAP_VLAN_MTU;
Index: sys/dev/fxp/if_fxpreg.h
===================================================================
--- sys/dev/fxp/if_fxpreg.h	(revision 183858)
+++ sys/dev/fxp/if_fxpreg.h	(working copy)
@@ -46,6 +46,7 @@
 #define	FXP_CSR_EEPROMCONTROL	14	/* eeprom control (2 bytes) */
 #define	FXP_CSR_MDICONTROL	16	/* mdi control (4 bytes) */
 #define	FXP_CSR_FLOWCONTROL	0x19	/* flow control (2 bytes) */
+#define	FXP_CSR_PMDR		0x1B	/* power management driver (1 byte) */
 #define	FXP_CSR_GENCONTROL	0x1C	/* general control (1 byte) */
 
 /*
Index: sys/dev/fxp/if_fxpvar.h
===================================================================
--- sys/dev/fxp/if_fxpvar.h	(revision 183858)
+++ sys/dev/fxp/if_fxpvar.h	(working copy)
@@ -193,6 +193,8 @@
 #define FXP_FLAG_DEFERRED_RNR	0x0200	/* DEVICE_POLLING deferred RNR */
 #define FXP_FLAG_EXT_RFA	0x0400	/* extended RFDs for csum offload */
 #define FXP_FLAG_SAVE_BAD	0x0800	/* save bad pkts: bad size, CRC, etc */
+#define FXP_FLAG_WOLCAP		0x1000	/* WOL supported */
+#define FXP_FLAG_WOL		0x2000	/* WOL active */
 
 /* Macros to ease CSR access. */
 #define	CSR_READ_1(sc, reg)		bus_read_1(sc->fxp_res[0], reg)