An experimental hack that makes head -r338518 boot from e.MMC via an microsd card adapter, in DDR52 mode at that
Mark Millard
marklmi at yahoo.com
Sat Sep 8 06:17:19 UTC 2018
The following hack demonstrates what is blocking
the use of e.MMC on an adapter on the Pine64+ 2GB
that I can test with (and likely more).
In essence the hack makes the code ignore "Failed
to set VCCQ" for DDR52 and so use the default
VCCQ and keep going.
# svnlite diff /usr/src/sys/dev/mmc/mmc.c
Index: /usr/src/sys/dev/mmc/mmc.c
===================================================================
--- /usr/src/sys/dev/mmc/mmc.c (revision 338518)
+++ /usr/src/sys/dev/mmc/mmc.c (working copy)
@@ -2226,7 +2226,7 @@
if (mmc_set_vccq(sc, ivar, timing) != MMC_ERR_NONE) {
device_printf(dev, "Failed to set VCCQ for "
"card at relative address %d\n", rca);
- continue;
+ //continue;
}
}
But that does not show what ended up executing instead.
So, giving more context:
if (timing == bus_timing_mmc_ddr52) {
/*
* Set EXT_CSD_BUS_WIDTH_n_DDR in EXT_CSD_BUS_WIDTH
* (must be done after switching to EXT_CSD_HS_TIMING).
*/
if (mmc_set_card_bus_width(sc, ivar, timing) !=
MMC_ERR_NONE) {
device_printf(dev, "Card at relative address "
"%d failed to set bus width\n", rca);
continue;
}
mmcbr_set_bus_width(dev, ivar->bus_width);
mmcbr_update_ios(dev);
if (mmc_set_vccq(sc, ivar, timing) != MMC_ERR_NONE) {
device_printf(dev, "Failed to set VCCQ for "
"card at relative address %d\n", rca);
//continue;
}
}
/* Set clock (must be done before initial tuning). */
mmcbr_set_clock(dev, max_dtr);
mmcbr_update_ios(dev);
. . .
power_class:
if (mmc_set_power_class(sc, ivar) != MMC_ERR_NONE) {
device_printf(dev, "Card at relative address %d "
"failed to set power class\n", rca);
}
This is inside the loop:
for (i = 0; i < sc->child_count; i++) {
in:
static int
mmc_calculate_clock(struct mmc_softc *sc)
in:
/usr/src/sys/dev/mmc/mmc.c
The result is:
mmc0: setting transfer rate to 52.000MHz (dual data rate timing)
mmc0: Failed to set VCCQ for card at relative address 2
mmcsd0: 125GB <MMCHC DJNB4R 0.7 SN 9F43B2E7 MFG 06/2016 by 21 0x0000> at mmc0 52.0MHz/4bit/32768-block
mmcsd0boot0: 4MB partion 1 at mmcsd0
mmcsd0boot1: 4MB partion 2 at mmcsd0
mmcsd0rpmb: 4MB partion 3 at mmcsd0
. . .
It boots to an operating multi-user environment just fine.
(I've not yet done things like buildworld or poudriere bulk.)
As evidence of DDR52 instead of High Speed:
# dd if=/dev/mmcsd0 of=/dev/null bs=1m
^C
811+0 records in
811+0 records out
850395136 bytes transferred in 20.315078 secs (41860294 bytes/sec)
===
Mark Millard
marklmi at yahoo.com
( dsl-only.net went
away in early 2018-Mar)
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