[Bug 199740] syscall __clear_cache (ARM_SYNC_ICACHE) does not achieve icache consistency

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https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=199740

Ian Lepore <ian at FreeBSD.org> changed:

           What    |Removed                     |Added
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                 CC|                            |ian at FreeBSD.org

--- Comment #1 from Ian Lepore <ian at FreeBSD.org> ---
The ARM ARM, in a rare example of lucidity, describes the register parameter
for cp15 cache operations thusly: "When the data is stated to be an MVA, it
does not have to be cache line aligned.

If these changes lead to something working that doesn't work without the
changes, I guess we need to figure out why.  It may imply that the caller to
the function is incorrectly converting a start/end tulple to start/len or
something along those lines.

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