DWC OTG TX path optimisation for 11-current

[Ian Lepore]

On Wed, 2015-08-26 at 08:26 +0200, Hans Petter Selasky wrote:
> On 08/25/15 21:51, Andreas Schwarz wrote:
> > On 24.08.15, Andreas Schwarz wrote:
> >
> >> With both kernels I was not able to reproduce the initial problem.
> >
> > By accident, today I run again into the problem (with r287086). 8(
> >
> > Aug 25 20:27:59 pizelot kernel: smsc0: warning: Failed to write register 0x114
> > Aug 25 20:45:32 pizelot kernel: smsc0: warning: Failed to read register 0x114
> > Aug 25 20:45:32 pizelot kernel: smsc0: warning: MII is busy
> > Aug 25 20:46:08 pizelot kernel: smsc0: warning: Failed to write register 0x114
> > Aug 25 20:46:14 pizelot kernel: smsc0: warning: Failed to read register 0x114
> > Aug 25 20:46:14 pizelot kernel: smsc0: warning: MII is busy
> > Aug 25 20:46:16 pizelot kernel: smsc0: warning: Failed to write register 0x114
> > Aug 25 20:46:46 pizelot kernel: smsc0: warning: Failed to read register 0x114
> > Aug 25 20:46:46 pizelot kernel: smsc0: warning: MII is busy
> > [...]
> >
> 
> It might seem like some process is using all CPU on core 0, so that USB 
> doesn't get a chance to run. I would suggest maybe moving the DWC OTG 
> fast IRQ handling to core #1. Is it possible you could enter kgdb, and 
> poke around which fast IRQ is doing work there?
> 

All interrupt handlers on armv6 run on core 0, always.  There's no way
to change that.

-- Ian