arm SMP on Cortex-A15

[Wojciech Macek]

Regarding 2., I would consider it as a proof of concept, or the least
invasive workaround - a lot of those flushes might not be necessary. But it
suggests, that there is a place in pmap where a situation of prefetching
old TLB can happen. I've seen some functions where, for example,
flush&pte_sync order is reversed, so this is the path that needs to be
investigated to get a proper fix.

Wojtek


2013/12/19 Olivier Houchard <mlfbsd at ci0.org>

> Hi Wojciech,
>
> On Thu, Dec 19, 2013 at 12:41:59PM +0100, Wojciech Macek wrote:
> > Hi,
> >
> > Finally, I'm able to run FreeBSD stable on Cortex-A15. The TLB issue
> which
> > was observed, was caused by an aggressive A15 feature called "L2 TLB
> > prefetch".
> >
>
> Wow that's great news !
>
> > There are 4 fixes that helped:
> > 0. Prerequisite, Olivier's patch for PCPU atomicity.
>
> Cool, I'll commit it, then.
>
> > 1. TEX remap - to be compliant with spec, TEX remap is used to configure
> > memory as Inner Shareable
> > 2. TLB flush SE - after each PTE modification and PTE_SYNC, there is no
> > guarantee that newly created entry is not overlapped by old value in TLB
> > cache. Do flush_SE to ensure proper mapping.
>
> Wow, I failed to realized we were missing so many flush. And I've read the
> pmap code to find any of those many many times. Great work !
>
>
> > 3. During context switch, ensure that tlb flush is executed after ttb is
> > changed. Clean BTB to be compliant with specs.
> >
> > Above patches can be found here
> >
> https://drive.google.com/folderview?id=0B-7yTLrPxaWteWFtWUQxVVNHVFk&usp=sharing
> >
> >
> > None of them is 100%-ready, but should work. Any comments and/or testing
> > are really appreciated.
> >
>
> Regards,
>
> Olivier
>