RFC: ARM related fixes - GIC, cache line size, PCI FDT & AHCI

[Nathan Whitehorn]

On 12/16/13 15:52, Nathan Whitehorn wrote:
> On 12/16/13 11:48, Zbigniew Bodek wrote:
>> Hello Everyone.
>>
>> We would like to submit some new patches recently developed by Semihalf.
>>
>> You can find them here:
>> http://people.freebsd.org/~zbb/Semihalf/12.2013/
>>
>> Detailed description is available in the commit logs but in general:
>>
>> -- 0001-Resolve-cache-line-size-using-CP15.patch
>>     - use cache line size acquired in runtime
>>
>> -- 0002-GIC-polarity-and-level-support.patch
>>     - suport for setting trigger level and polarity in GIC
>>
>> -- 0003-Add-PCI-FDT-interrupt-trigger-polarity-parsing.patch
>>     - trigger and polarity parsing for PCI FDT interrupts
>>
>> -- 0004-Do-not-attach-to-bridges-in-AHCI-driver.patch
>> -- 0005-Use-only-mapped-BIOs-on-ARM.patch
>>     - Two patches enabling the AHCI driver on ARM chips
>>
>>
>> We will appreciate if you could post your comments and/or remarks by the
>> end of this week when we plan to commit the changes.
>>
>> Best regards
>> zbb
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>
> Can you hold off on 
> 0003-Add-PCI-FDT-interrupt-trigger-polarity-parsing.patch for the time 
> being? I'm restructuring this code at the moment.
> -Nathan
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This is done now. I have not updated the ARM code, because I don't know 
how it is supposed to work, but you can take a look at r259513 to 
powerpc/ofw/ofw_pci.c to see how the new stuff works. It relies on some 
device (nexus, for example) implementing OFW_BUS_CONFIG_INTR(), which 
takes an IRQ and a sense code, but that seems to be wrapped up in a lot 
of ARM-specific stuff.

If you like, I can just write a piece of bridge code, but I don't want 
to interfere with in-flight things on your end.
-Nathan