RFC: ARM related fixes - GIC, cache line size, PCI FDT & AHCI

[Ganbold Tsagaankhuu]

Zbigniew,


On Tue, Dec 17, 2013 at 1:48 AM, Zbigniew Bodek <zbb at semihalf.com> wrote:

> Hello Everyone.
>
> We would like to submit some new patches recently developed by Semihalf.
>
> You can find them here:
> http://people.freebsd.org/~zbb/Semihalf/12.2013/
>
> Detailed description is available in the commit logs but in general:
>
> -- 0001-Resolve-cache-line-size-using-CP15.patch
>    - use cache line size acquired in runtime
>
> -- 0002-GIC-polarity-and-level-support.patch
>    - suport for setting trigger level and polarity in GIC
>


It seems Krait SoC's PPIs are all edge triggered according to linux code,
and I was using simpler one line reg write method in this regard.
I will try to test it in couple of days.

thanks,

Ganbold



>
> -- 0003-Add-PCI-FDT-interrupt-trigger-polarity-parsing.patch
>    - trigger and polarity parsing for PCI FDT interrupts
>
> -- 0004-Do-not-attach-to-bridges-in-AHCI-driver.patch
> -- 0005-Use-only-mapped-BIOs-on-ARM.patch
>    - Two patches enabling the AHCI driver on ARM chips
>
>
> We will appreciate if you could post your comments and/or remarks by the
> end of this week when we plan to commit the changes.
>
> Best regards
> zbb
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