RFC: ARM related fixes - GIC, cache line size, PCI FDT & AHCI

[Warner Losh]

On Dec 16, 2013, at 10:48 AM, Zbigniew Bodek wrote:

> Hello Everyone.
> 
> We would like to submit some new patches recently developed by Semihalf.

Thanks for your efforts here. Would there be a need to MFC these patches to 10 and/or 9?

> You can find them here:
> http://people.freebsd.org/~zbb/Semihalf/12.2013/
> 
> Detailed description is available in the commit logs but in general:
> 
> -- 0001-Resolve-cache-line-size-using-CP15.patch
>   - use cache line size acquired in runtime

This looks good (assuming the register definitions are good, I didn't verify them). Might be useful to publish these values to userland somehow, maybe via a sysctl. This is option, but would be nice to have.

Would also be good to have USB_ALIGN kassert if using USB and this value is < that macro.

Do other, older CPUs need similar decoding, or are the hard-wired values good?

> -- 0002-GIC-polarity-and-level-support.patch
>   - suport for setting trigger level and polarity in GIC

This one seems to be OK, but is complicated enough that more eyeballs and testing would be good....

> -- 0003-Add-PCI-FDT-interrupt-trigger-polarity-parsing.patch
>   - trigger and polarity parsing for PCI FDT interrupts

This patch might conflict.

+		if (trig)
+			*trig = tmp_trig;
+		if (pol)
+			*pol = tmp_pol;

Are not zero values also valid?

> -- 0004-Do-not-attach-to-bridges-in-AHCI-driver.patch

I'd add the word 'PCI' before bridge in the comment, otherwise this looks good.

> -- 0005-Use-only-mapped-BIOs-on-ARM.patch

A comment about what MVA is would be useful.. Otherwise does what it says.

>  - Two patches enabling the AHCI driver on ARM chips

I didn't see these. Did I miss something? Or is the unmapped stuff all it takes?

> We will appreciate if you could post your comments and/or remarks by the
> end of this week when we plan to commit the changes.
> 
> Best regards
> zbb
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