FreeBSD/armv6z/clang on Raspberry Pi 512MB (with U-Boot + ubldr)

[Daisuke Aoyama]

>PTE sync - related part, Im not sure it's strictly required. We use WT 
>caches for page tables
>so we should be OK without implicit sync operations for them. I hope 
>somebody
>more clueful can confirm/disprove this.

Some digging, I notice "Invalidate Entire Instruction Cache" works without 
segfault.
So, Invalidate D-cache is no effect :)

It seems following should work for this issue:

        mov     r0, #0
        mcr     p15, 0, r0, c7, c5, 0           /* Invalidate Entire 
Instruction Cache */
        mcr     p15, 0, r0, c7, c10, 4          /* Data Synchronization 
Barrier */

Try this code instead of CF_ICACHE_SYNC.
I don't know side effect of Invalidate I-cache, but it works.
Also I don't know whether DSB is required or not.

For test, using NFS or HDD/SDD is BAD idea for system stress.
You must use SD(mmc) or USB memory. Serial console is recommended for 
interrupt test.
Here is simple test from serial console:

# rm -rf /var/db/portsnap /usr/ports
# mkdir /var/db/portsnap
# portsnap fetch
# portsnap extract
# cd /usr/ports/shells/bash
# make BATCH=y

If your kernel is really stable, it should finish without any problems with 
SD/mmc.

----------------------------------------------------------------------
--- sys/arm/arm/swtch.S (revision 244663)
+++ sys/arm/arm/swtch.S (working copy)
@@ -130,7 +130,11 @@
        /* Switch to lwp0 context */

        ldr     r9, .Lcpufuncs
-#if !defined(CPU_ARM11) && !defined(CPU_CORTEXA) && !defined(CPU_MV_PJ4B)
+#if defined(CPU_ARM1176)
+       mov     r0, #0
+       mcr     p15, 0, r0, c7, c5, 0           /* Invalidate Entire 
Instruction Cache */
+       mcr     p15, 0, r0, c7, c10, 4          /* Data Synchronization 
Barrier */
+#elif !defined(CPU_CORTEXA) && !defined(CPU_MV_PJ4B)
        mov     lr, pc
        ldr     pc, [r9, #CF_IDCACHE_WBINV_ALL]
 #endif
@@ -352,7 +356,11 @@
        cmpeq   r0, r5                          /* Same DACR? */
        beq     .Lcs_context_switched           /* yes! */

-#if !defined(CPU_ARM11) && !defined(CPU_CORTEXA) && !defined(CPU_MV_PJ4B)
+#if defined(CPU_ARM1176)
+       mov     r0, #0
+       mcr     p15, 0, r0, c7, c5, 0           /* Invalidate Entire 
Instruction Cache */
+       mcr     p15, 0, r0, c7, c10, 4          /* Data Synchronization 
Barrier */
+#elif !defined(CPU_CORTEXA) && !defined(CPU_MV_PJ4B)
        /*
         * Definately need to flush the cache.
         */
----------------------------------------------------------------------

Thanks.
-- 
Daisuke Aoyama