Partial cacheline flush problems on ARM and MIPS

[Adrian Chadd]

Right, that's what Linux does for ARM/MIPS. It just sets the minimum
allocation size to be cache line sized. That way they didn't have to
fix their USB and network stack code.

.. or, we could fix the USB stack code by saying that anything being
used as a DMA buffer needs to be minimum cache line size (which can be
determined at run time if appropriate) and make the minimum allocation
that.

Then either it uses a separate allocation for each buffer or it
allocates one big set of buffers and chops them up in at least "cache
line size" bits.

That reminds me, I should do that to the descriptor allocation in the
Atheros driver - ie, round up the descriptor allocation size to a
multiple of a cache line. That way DMAs don't conflict with the next
DMAed buffer..


Adrian