Performance of SheevaPlug on 8-stable

[Maks Verver]

On 03/06/2010 10:17 PM, Bernd Walter wrote:
> Such massive speed difference sounds a bit like cache problems.

On 03/06/2010 11:26 PM, M. Warner Losh wrote:
> Sounds a lot like ICACHE isn't being enabled, since a 3-liner like 
> this should be executing entirely out of cache after the first 
> instruction in main prefetches the cache line.

Thanks for the quick responses! I think the both of you are right. I
didn't realize the cache could be turned off at all, but the boot output
shows:

  CPU: Feroceon 88FR131 rev 1 (write-through core)
    WB enabled EABT branch prediction enabled
    16KB/32B 4-way Instruction cache
    16KB/32B 4-way write-back-locking-C Data cache

This is different from the output on the wiki (which instructions I
followed, to some extent) at http://wiki.freebsd.org/FreeBSDMarvell:

CPU: ARM926EJ-S rev 0 (ARM9EJ-S core)
  DC enabled IC enabled WB enabled EABT branch prediction enabled
  32KB/32B 1-way Instruction cache
  32KB/32B 4-way write-back-locking-C Data cache

Note that this guy is not running a SheevaPlug; the CPU is different.
But it's clear enough that on my system both processor caches are
disabled (even though they are correctly identified) and this is
understandably catastrophic for performance. It's good to have that
figured out at least. :-)

The logical next question is: why aren't these caches enabled? How is
this supposed to work? Is the bootloader supposed to enable the cache,
or the kernel? If the kernel, why isn't it doing this? (If it's the
bootloader's task, then it's strange that the Linux kernel has no
trouble enabling the cache with the same bootloader).

Kind regards,
Maks Verver.