f_offset

[David Schultz]

On Sun, Apr 13, 2008, Jeff Roberson wrote:
> Thanks.  I hadn't seen that.  Do you know which manual and section states 
> this?  I was intending to simply use cmpxchg8b but it sounds like that may 
> not be necessary.  We still have to handle other 32bit archs like powerpc 
> and mips but I'm not sure if any of those are SMP.

Usually single-instruction writes to within a single cache line
are atomic, and cache lines are often 128+ bits. The trouble is
that 32-bit architectures may not have 64-bit store instructions
at all.

I know that 32-bit powerpc processors don't have 64-bit
compare-and-swap atomic ops. They do have a stmw instruction,
which is sort of equivalent to i386's 'rep stosd', and can store
64 bits in one instruction, but I doubt that that's atomic.

Maybe the best strategy would be to say something like:

#ifdef atomic_set_64
	atomic_set_64(&fp->f_offset, uio_resid);
#else
	mtx_lock(fp->f_mtx);
	fp->f_offset = uio_resid;
#endif

(Worse) alternatives:

- Generic (very slow) atomic_set_64 implemented in terms of hashed
  mutexes.

- Add a level of indirection to implement the 64-bit update in terms
  of atomic pointer ops, i.e.:
	newoffset = uio_resid;
	membar();
	atomic_set_ptr(&fp->f_offsetp, &newoffset);
  The idea here is that pointer-size writes are often atomic even
  if uint64_t-size writes aren't.