Scheduler fixes for hyperthreading

Colin Percival cperciva at freebsd.org
Sat May 21 21:35:43 PDT 2005


Marcel Moolenaar wrote:
> There are a lot of variables that need to be taken into account and
> those variables do not necessarily map perfectly from a P4 to an I2.
> Sharing of the L1 cache is not a sufficient condition to create a
> side-channel for timing attacks. A reliable time source with enough
> precision is also necessary (as you and Stephan have pointed out).
> The precision of the time source depends on latencies of the various
> cache levels and the micro-architectural behavior of the processor.

Point taken.  I maintain, however, that it is much better to make
"information can leak between these processors" a machine-independent
concept which is handled appropriately by the scheduler (with the
necessary machine-dependent code to specify *which* sets of processors,
if any, have such leakage).

Colin Percival


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