Scheduler fixes for hyperthreading

Marcel Moolenaar marcel at xcllnt.net
Sat May 21 21:21:48 PDT 2005


On May 21, 2005, at 6:59 PM, Colin Percival wrote:

> Marcel Moolenaar wrote:
>> On May 21, 2005, at 5:49 PM, Colin Percival wrote:
>>> Put simply, threads which share a processor core can monitor each 
>>> others'
>>> memory access patterns, so we need to ensure that such co-scheduling
>>> never
>>> happens between threads which have different privileges.
>>
>> I'll be studying your paper to see if it can be shown that the HT
>> implementation in Itanium is affected as well.
>
> My understanding is that there are no currently released ia64 
> processors
> with hyperthreading support, but that some future ia64 processor(s) are
> likely to be affected.

There are a lot of variables that need to be taken into account and
those variables do not necessarily map perfectly from a P4 to an I2.
Sharing of the L1 cache is not a sufficient condition to create a
side-channel for timing attacks. A reliable time source with enough
precision is also necessary (as you and Stephan have pointed out).
The precision of the time source depends on latencies of the various
cache levels and the micro-architectural behavior of the processor.

All I'm saying is: remain precise and careful.

-- 
  Marcel Moolenaar         USPA: A-39004          marcel at xcllnt.net



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