piix4 and C2: patch for BRLD_EN_BM/ACPI_BITREG_BUS_MASTER_RLD

[Andriy Gapon]

Another patch for acpi_cpu code related to PIIX4 chipset.

We do not support C3 with this chipset and as such we never touch
ACPI_BITREG_BUS_MASTER_RLD when running on it. It's also possible
(probable) that we never reset ACPI_BITREG_BUS_MASTER_STATUS (because of
CPU_QUIRK_NO_BM_CTRL).
So, if BIOS configures ACPI_BITREG_BUS_MASTER_RLD to 1 and
ACPI_BITREG_BUS_MASTER_STATUS gets set to 1, we would get a situation
where the system would always immediately break out of C2 state should
we ever attempt to enter it.

Actually, ACPI spec says that bus master activity need not break out of
C2 state (only interrupts must do that).

Given all of the above, it seems to be safe and desired to reset
ACPI_BITREG_BUS_MASTER_RLD to zero with this chipset.

The patch is successfully tested on a real system that exhibited the
above behavior (immediate backout from cx_lowest of C2 to C1).


-- 
Andriy Gapon
-------------- next part --------------
diff --git a/sys/dev/acpica/acpi_cpu.c b/sys/dev/acpica/acpi_cpu.c
index 3c4ad4e..73f5e9c 100644
--- a/sys/dev/acpica/acpi_cpu.c
+++ b/sys/dev/acpica/acpi_cpu.c
@@ -1062,6 +1062,10 @@ acpi_cpu_quirks(void)
 	 *
 	 * Also, make sure that all interrupts cause a "Stop Break"
 	 * event to exit from C2 state.
+	 * Also, BRLD_EN_BM (ACPI_BITREG_BUS_MASTER_RLD in ACPI-speak)
+	 * should be set to zero, otherwise it causes C2 to short-sleep.
+	 * PIIX4 doesn't properly support C3 and bus master activity
+	 * need not break out of C2.
 	 */
 	case PCI_REVISION_A_STEP:
 	case PCI_REVISION_B_STEP:
@@ -1074,10 +1078,16 @@ acpi_cpu_quirks(void)
 	    val = pci_read_config(acpi_dev, PIIX4_DEVACTB_REG, 4);
 	    if ((val & PIIX4_STOP_BREAK_MASK) != PIIX4_STOP_BREAK_MASK) {
 		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
-		    "PIIX4: enabling IRQs to generate Stop Break\n"));
+		    "acpi_cpu: PIIX4: enabling IRQs to generate Stop Break\n"));
 	    	val |= PIIX4_STOP_BREAK_MASK;
 		pci_write_config(acpi_dev, PIIX4_DEVACTB_REG, val, 4);
 	    }
+	    AcpiGetRegister(ACPI_BITREG_BUS_MASTER_RLD, &val);
+	    if (val) {
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
+		    "acpi_cpu: PIIX4: reset BRLD_EN_BM\n"));
+		AcpiSetRegister(ACPI_BITREG_BUS_MASTER_RLD, 0);
+	    }
 	    break;
 	default:
 	    break;